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AMIS-53050 Frequency Agile Transceiver
Data Sheet
AMIS-53050 Frequency Agile Transceiver Data Sheet
AMI Semiconductor - Jan. 07, M-20639-002 www.amis.com
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AMIS-53050 Frequency Agile Transceiver
Table of Contents
Data Sheet
1.0 Overview of the AMIS-53050.............................................................................................................................................................. 5 1.1 Typical Applications .......................................................................................................................................................................... 5 1.2 Key Features .................................................................................................................................................................................... 5 1.3 Technical Features ........................................................................................................................................................................... 5 1.4 Circuit Overview................................................................................................................................................................................ 6
1.4.1. Transmitter ..........................................................................................................................................................................................................6 1.4.2. Receiver ...............................................................................................................................................................................................................6
2.0 Operational Specifications ................................................................................................................................................................ 8 2.1 Absolute Maximum Ratings .............................................................................................................................................................. 8 2.2 Recommended Operating Conditions ............................................................................................................................................... 8
2.2.1. Parametric Voltage and Current Levels ............................................................................................................................................................8
2.3 Operational Specifications ................................................................................................................................................................ 9 3.0 Block Diagrams ................................................................................................................................................................................ 12
3.1 AMIS-53050 Overall Block Diagram............................................................................................................................................... 12
3.2 Package.......................................................................................................................................................................................... 12
3.2.1. Pin Definition .....................................................................................................................................................................................................12 3.2.2. Block Diagram/Pin Definition...........................................................................................................................................................................13 3.2.3. Physical Characteristics...................................................................................................................................................................................14
4.0 Acronyms.......................................................................................................................................................................................... 15 5.0 Hardware Description ...................................................................................................................................................................... 16 5.1 Frequency....................................................................................................................................................................................... 16 5.2 Receiver.......................................................................................................................................................................................... 19
5.2.1. Receiver Low Noise Amplifier (LNA)...............................................................................................................................................................20 5.2.2. IF Filter ...............................................................................................................................................................................................................21 5.2.3. Data Filter...........................................................................................................................................................................................................21
5.3 Transmitter...................................................................................................................................................................................... 21 5.4 Single Antenna Option .................................................................................................................................................................... 22 5.5 Peak................................................................................................................................................................................................ 24 5.6 ADC ................................................................................................................................................................................................ 25 5.7 Control Interface Serial Bus ............................................................................................................................................................ 25 5.8 TX/RX Data Interface Serial Bus .................................................................................................................................................... 26 5.9 System Clock.................................................................................................................................................................................. 28 5.10 Power and Grounds ...................................................................................................................................................................... 29 5.11 Design Suggestions ...................................................................................................................................................................... 29 6.0 User's Guide ..................................................................................................................................................................................... 31 6.1 Control Serial Interface Bus Description ......................................................................................................................................... 31
6.1.1. Control Interface Protocol................................................................................................................................................................................31
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
6.1.2. Serial Control Interface: Configuration...........................................................................................................................................................34 6.1.3. 3-Wire Interface Mode.......................................................................................................................................................................................35 2 6.1.4. I C Interface .......................................................................................................................................................................................................37
6.2 Command Register ......................................................................................................................................................................... 40
6.3 Functional Flow Diagrams.............................................................................................................................................................. 41
6.4 Frequency....................................................................................................................................................................................... 46
6.4.1. Frequency Control ............................................................................................................................................................................................46 6.4.2. 10kHz Oscillator ................................................................................................................................................................................................50 6.4.3. System Clock.....................................................................................................................................................................................................50 6.4.4. Quick Start .........................................................................................................................................................................................................51 6.4.5. Self Calibration..................................................................................................................................................................................................51
6.5 Receiver.......................................................................................................................................................................................... 54
6.5.1. Receiver Circuit Brief Overview ......................................................................................................................................................................54
6.6 Transmitter ..................................................................................................................................................................................... 64
6.6.1. TX Config ...........................................................................................................................................................................................................65 6.6.2. Output Power.....................................................................................................................................................................................................65 6.6.3. Preamble Length ...............................................................................................................................................................................................66 6.6.4. FM Transmit Data Shaping...............................................................................................................................................................................66
6.7 Idle .................................................................................................................................................................................................. 66
6.7.1. Idle Config..........................................................................................................................................................................................................67 6.7.2. Sniff Mode Operation........................................................................................................................................................................................68 6.7.3. Burst Transmit Data..........................................................................................................................................................................................72 6.7.4. Housekeeping....................................................................................................................................................................................................74
6.8 Idle Return ...................................................................................................................................................................................... 75 6.9 EE ................................................................................................................................................................................................... 76
6.9.1. Write EE .............................................................................................................................................................................................................76 6.9.2. Load EE..............................................................................................................................................................................................................76
6.10 Calibrate ....................................................................................................................................................................................... 76
6.10.1. Internal Trim ....................................................................................................................................................................................................77 6.10.2. Calibrate Quick Start Oscillator .....................................................................................................................................................................78 6.10.3. Calibrate 10kHz Oscillator..............................................................................................................................................................................78 6.10.4. Calibrate PLL ...................................................................................................................................................................................................78 6.10.5. Calibrate LNA ..................................................................................................................................................................................................78
6.11 ROM 2 REGS ............................................................................................................................................................................... 79 6.12 Chip Reset .................................................................................................................................................................................... 79 6.13 ADC Conversion ........................................................................................................................................................................... 79
6.13.1. ADC Conversion Results................................................................................................................................................................................80 6.13.2. Single ADC Conversion..................................................................................................................................................................................81 6.13.3. Continuous ADC Conversion.........................................................................................................................................................................81
7.0 Data Interface.................................................................................................................................................................................... 81
7.1.1. Chip Address MSB1..........................................................................................................................................................................................83 7.1.2. Chip Address LSB.............................................................................................................................................................................................83 7.1.3. Data Rate/Format ..............................................................................................................................................................................................83 7.1.4. General Options A.............................................................................................................................................................................................84 7.1.5. General Options B.............................................................................................................................................................................................85 7.1.6. Start of Frame....................................................................................................................................................................................................86 7.1.7. Data Rate 1.........................................................................................................................................................................................................86 7.1.8. Data Rate 0.........................................................................................................................................................................................................86 7.1.9. CRC Polynomial ................................................................................................................................................................................................87 7.1.10. Default Length of Packet ................................................................................................................................................................................87 7.1.11. Broadcast ID 1 .................................................................................................................................................................................................87 7.1.12. Broadcast ID 0 .................................................................................................................................................................................................87
7.2 TX/RX Data Interface Protocol........................................................................................................................................................ 88
7.2.1. AMIS-53050 in Master Mode.............................................................................................................................................................................91 7.2.2. AMIS-53050 in Slave Mode ...............................................................................................................................................................................92
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
7.2.3. Manchester Operation ......................................................................................................................................................................................92 7.2.4. Packet Framing .................................................................................................................................................................................................93 7.2.5. Use ID .................................................................................................................................................................................................................93 7.2.6. Length of Packet Enable ..................................................................................................................................................................................94 7.2.7. CRC Enable........................................................................................................................................................................................................94 7.2.8. SOF Byte ............................................................................................................................................................................................................94 7.2.9. Timing Diagrams for Various Packet Framing Modes...................................................................................................................................95
8.0 General System Functions .............................................................................................................................................................. 98 8.1 Pull-up Disable................................................................................................................................................................................ 98 8.2 Brown-Out POR .............................................................................................................................................................................. 98 8.3 Temperature Sensor ....................................................................................................................................................................... 98
8.3.1. Crystal Temperature Compensation ...............................................................................................................................................................99
8.4 Software.......................................................................................................................................................................................... 99
8.4.1. AMIS Part Revision Code .................................................................................................................................................................................99
9.0 Built-in Test Functions................................................................................................................................................................... 100 9.1 TM Unlock Register ...................................................................................................................................................................... 100 9.2 Test Registers............................................................................................................................................................................... 100
9.2.1. IF Amp Manual Trim A ....................................................................................................................................................................................100 9.2.2. IF Amp Manual Trim B ....................................................................................................................................................................................100 9.2.3. PLL Manual Trim .............................................................................................................................................................................................100 9.2.4. PLL Test Modes...............................................................................................................................................................................................100 9.2.5. Power Down RF Sections...............................................................................................................................................................................101 9.2.6. Analog Test Mode ...........................................................................................................................................................................................101 9.2.7. RF Test Modes.................................................................................................................................................................................................101 9.2.8. Analog Test MUX.............................................................................................................................................................................................101 9.2.9. RF Test MUX ....................................................................................................................................................................................................101 9.2.10. Digital Test MUX A ........................................................................................................................................................................................102 9.2.11. Digital Test MUX B ........................................................................................................................................................................................102 9.2.12. Digital Test MUX C ........................................................................................................................................................................................103 9.2.13. Digital Test Mode A.......................................................................................................................................................................................103 9.2.14. Digital Test Mode B.......................................................................................................................................................................................103 9.2.15. Digital Test Mode C.......................................................................................................................................................................................103 9.2.16. Digital Test Mode D.......................................................................................................................................................................................103 9.2.17. Memory Test Mode Address ........................................................................................................................................................................103 9.2.18. Memory Test Mode Data...............................................................................................................................................................................103
10.0 Register Definition........................................................................................................................................................................ 104 11.0 Applications.................................................................................................................................................................................. 106 12.0 Ordering Information.................................................................................................................................................................... 107 13.0 Company or Product Inquiries .................................................................................................................................................... 107
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
1.0 Overview of the AMIS-53050
The AMIS-53050 is a highly integrated and configurable single-chip wireless transceiver and is based on AMI Semiconductor's ASTRICTM wireless solutions platform. It is ideally suited for multi-channel (sub-1GHz), low to moderate data rate, low power, narrow band wireless applications in the automotive and industrial markets. The device provides for a number of data modulation schemes, including frequency shift key (FSK), Gaussian FSK (GFSK) and on/off shift key (OOK) modulation, respectively. The AMIS-53050 can be easily interfaced to a baseband processor via a serial interface bus.
1.1 Typical Applications * * * * * * * * Wireless sensors RFID Remote monitoring Access control and security Keyless entry Mobile wireless data terminals Tire pressure monitors Wireless toys
1.2 Key Features * * * * * * * * * * * * * Very low power single-chip CMOS transceiver Patented Quick Start crystal oscillator Low power receive Sniff ModeTM Periodic transmit using burst mode Internal low power 10kHz oscillator Internal self-calibration functions SPI/I2C interface bus 3-wire/4-wire serial data interface Two analog to digital converter channels Internal fractional N frequency synthesizer OOK / FSK / Gaussian FSK (BT = 1) modulation Internal temperature sensor Minimal external components
1.3 Technical Features * * * * * * * * * Operating voltage range: 2.2 to 3.3V Operating temperature range: -40 to +85oC Operating frequency range: 300 - 960MHz Data rate: o 1 to 19.2kbps (OOK) o 2 to 128kbps (FSK/GFSK) Transmit output power: o +15dBm max (high power mode) o +0dBm max (low power mode) Transmit current: 50mA typical (15dBm) Receiver sensitivity o -115dBm (OOK @ 1kbps) o -105dBm (FSK @ 20kbps) Receiver current: 12mA (continuous) Minimum RX energy detect time: 130uS (sniff mode)
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AMIS-53050 Frequency Agile Transceiver
1.4 Circuit Overview 1.4.1. Transmitter
Data Sheet
In the AMIS-53050, a pre-driver and a class E power amplifier are used to output the OOK- or FSK-modulated radio frequency signals. The class E power amplifier has two output power ranges aimed at realizing high output power efficiency. The output power level is programmable, the maximum value for these two ranges being 0dBm and +15dBm, respectively. The class E power amplifier provides maximum output power of +12dBm to +15dBm in the frequency range of 300MHz to 915MHz. The transmitted data can be NRZ or Manchester encoded. Data rates for OOK modulation can be as high as 19.2kbps, while data rates for FSK/GFSK modulation can be as high as 128kbps. The deviation of the RF carrier frequency for the FSK modulation is programmable, typically being one half to one times the data rate. The transmit data output can be wave shaped with a Gaussian format. This can reduce the occupied bandwidth of the signal. Power to the transmitter PA can be ramped during power-up and power-down transitions, respectively, in order to reduce signal frequency splatter.
1.4.2. Receiver The AMIS-53050 has single receive and transmit channels, respectively, which can be connected to individual antennas or alternatively to a single antenna, using external components. A single antenna configuration will have reduced performance, receiver sensitivity and/or transmit output power. The receiver uses four different methods to receive and recover data that has been on/off shift key or frequency shift key modulated. The FSK/GFSK data is recovered using either a phase-locked loop (PLL) or a Fast Fourier transform (FFT) circuit, in conjunction with a clock and data recovery (CDR) circuit. The OOK data is recovered using a received signal strength indicator (RSSI) circuit. It is suggested that the CDR circuit be used when receiving OOK signals as well.
1.4.2.1.
On/Off Shift Key Modulation
The AMIS-53050 uses a logarithmic RSSI detector to recover the data from the on/off shift key modulated waveforms. Data rates can be as high as 19.2kbps. The device has eight discrete data filters for common baud rates. The receiver can detect either NRZ or Manchester encoded data. The single Byte command ROM2REGs will change the slice filter settings and the CDR settings when one of the standard data rates is selected.
1.4.2.2.
Low Data Rate Frequency Shift Key Modulation
The AMIS-53050 uses a digital PLL detector to recover the received frequency shift key data below 20kbps. The recovered data waveform is in turn applied to the CDR circuit to produce the digital data and a synchronized clock. The receiver can detect either NRZ or Manchester encoded data. The single byte command ROM2REGs will change the CDR settings when one of the standard data rates is selected.
1.4.2.3.
High Data Rate Frequency Shift Key Modulation
An integrated FFT circuit is used to recover the received frequency shift key modulated waveforms when the data rate is higher than 20kbps. The data rate can be as high as 128kbps. The demodulated data waveform is in turn applied to the clock and data recovery circuit to produce the digital data and a synchronized clock. The receiver can detect either NRZ or Manchester encoded data. The single byte command ROM2REGs will change the CDR settings when one of the standard data rates is selected.
1.4.2.4.
Clock and Data Recovery
The AMIS-53050 uses a CDR circuit that is linked to the frequency shift key or on/off shift key data detector circuits to recover the data stream. The CDR circuit synchronizes a clock with the data rate of the received data. The CDR function is a critical element for the recovery of high data rate (>20kbps) FSK signals, while data can be recovered without the CDR function for low data rate FSK and OOK signals, respectively. It is recommended, however, that the CDR function be used with all receiver data recovery methods.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
1.4.2.5.
Manchester Data Encoding
The AMIS-53050 can encode the data as NRZ or Manchester. Manchester encoding can improve the communication link as the encoding removes long time periods with the same level of multiple bits, without a data edge transition. Manchester encoding will require that the data rate be half of the NRZ data rate.
1.4.2.6.
Oscillators
The AMIS-53050 requires a single external crystal working with the internal VCO and PLL to generate frequencies from 300MHz to 960MHz. The AMIS-53050 has internal capacitors, which eliminate the need for external load capacitors when using a typical 24MHz external crystal. The VCO requires an external inductor and capacitor (in conjunction with the internal capacitance) and user programming of the device in order to produce the desired transmit or receive RF frequency. Due to parasitics associated with an external capacitor, it is recommended that only a coil be used with the VCO unless the circuit cannot achieve the desired frequency without a capacitor. A patented Quick Start circuit is used to force the crystal oscillator to the desired frequency in microseconds rather than in milliseconds. A low power internal 10kHz oscillator provides the timing for sniff, burst and housekeeping modes of operation. In this case, based on integrated self-calibration circuitry, a frequency tolerance of +/- 2% can be achieved. Crystal frequencies other than 24MHz may be used; however, this option is not recommended because: * * * * * The Quick Start feature will not function The algorithm for determining the frequency register values will change The algorithm for determining the data rate register values will change The algorithm for determining the FSK modulation deviation register values will change The RF frequency operational range of the device will change
1.4.2.7.
Interface Serial Bus
The AMIS-53050 has separate interfaces for data and control. The transfer of TX/RX data between the transceiver and an external host controller is performed using a 3-wire serial interface or a 4-wire SPI compatible serial interface, respectively. Control information is either written to or read from the appropriate register using either a 3-wire serial interface (only available with the AMIS-53050-002 2 version) or a 2-wire I C compatible serial interface. Once the data pertaining to the configuration of various modes of operation, such as transmit, receive, sniff, etc., is written to the configuration register, placing the device into one of these specific modes is accomplished via a single write command.
TX/RX Data Interface
The transmit or receive data interface can be programmed to be either a proprietary 3-wire serial interface or a 4-wire SPI compatible serial interface, respectively. The data interface can be set up for data transfer to a buffer or alternatively, for streaming data. In the buffered data mode, the device can be configured as a master or a slave. However, it must be configured as a master in order to process streaming data. When the transceiver is first powered on, an external host controller can be used to configure the type of interface (3-wire or I2C) by simply writing the desired protocol to the AMIS-53050. As long as power is not removed from the device, this configuration is maintained. The AMIS-53050 is always a slave device for the control interface. The AMIS-53050-002 version does not bond the SSN 2 signal to an external pin of the AMIS-53050 pin. This version must use the I C interface bus and the SSN line defaults to the correct level to enable the I2C interface bus with the first write operation.
Control Interface
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AMIS-53050 Frequency Agile Transceiver
2.0 Operational Specifications
2.1 Absolute Maximum Ratings
Table 1: Absolute Maximum Ratings Symbol Parameter Vdd Vin Iin Tstrg Tlead ESDHBM ESDCDM ESDMM DC supply voltage Input pin voltage Input pin current Storage temperature Lead temperature Human body model Charged-device model Machine model
Data Sheet
Min. -0.3 -0.3 -10.0 -55
Max. 3.6 Vdd+0.3 10.0 150 300 2.25 1000 175
Units V V mA C C kV V V
Notes
25C SSOP 10 sec
2.2 Recommended Operating Conditions
Table 2: Operating Conditions Symbol Parameter Vdd DC supply Standby current (off current) Standby current (off current) Ground Ambient temperature 0.0 -40
Min. 2.2
Max. 3.3 0.8 0.2 0.0 85
Units V uA uA V C
Notes (AMIS-53050-001) (AMIS-53050-002)
(1)(2) (1)(2)
Idds
Idds Vss Ta
Notes: 1. 2.
Stand-by current is specified at room temperature, with all analog cells in power-down mode, logic powered up with no clocks running, all outputs unloaded and inputs set either high or low (no floating inputs). The lowest receiver current is achieved when using the AMIS-53050-001 version with the internal digital regulator and a 100uF capacitor on Pin 22 (SSN/CoreReg).
2.2.1. Parametric Voltage and Current Levels (Test data for various device currents assumes a static set-up, with measurements performed while static data is applied to the device)
2.2.1.1.
Inputs Iil (1) Max. (V) 1.0 1.0 Min. uA 0.0 0.0 0.0 Max. uA 1.0 1.0 1.0 Min. uA -1.0 -30 -1.0 Iih (1) Max. uA 0.0 -90 0.0
Table 3: Pin Input Parameters Pin Min. (V) AI DISU DISC
Notes: 1. 2. 3.
Vil Max. (V) 0.3 0.3 Min. (V) 0.8 0.8
Vih
Notes (2)
Analog input CMOS with pull up Schmitt CMOS Schmitt
0.0 0.0
Iil and Iih are tested at Vdd = VDDmax volts. Not tested at temperatures lower than room temperature PU = pull-up, PD = pull-down, SC = Schmitt, SU = Schmitt & pull-up and SD = Schmitt and pull-down. CMOS values are 'Vin * VDD' and TTL values are absolute voltages.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
2.2.1.2.
Outputs Iol (1,3) Min. Max. mA mA 2 Ioh (2,3) Min. mA -2 Max. mA Analog outputs CMOS
Table 4: Pin Output Parameters Vol Voh Pin (1) (2) Min. Max. Min. Max. (V) (V) (V) (V) AO DO
Notes: 1. 2. 3.
Notes
0
0.4
Vdd-.4
Vol, Iol are tested at Vdd = VDDmin volts unless otherwise stated Voh, Ioh are tested at Vdd = VDDmin volts unless otherwise stated Polarity on currents indicates direction of current: (+) for sinking and (-) for sourcing
2.2.1.3.
I/O Pins Vol V Max. (1) 0.4 Voh V Min. (2) Vdd-.4 Iol mA Min. (1) 2 Ioh mA Min. (2) -2 Iozl uA Max. (3) 1 Iozh uA Max. (3) -1
Table 5: I/O Pin Parameters Pin AIO DIO
Notes: 1. 2. 3.
Vil V Min.
Vil V Max.
Vih V Min.
Vih V Max.
Vol V (1)
Voh V (2)
Notes
0
0.3
0.8
1
0
Vdd
Schmitt
Vol, Iol are tested at Vdd = 3.1V. Voh, Ioh are tested at Vdd = 3.1V. Ioz is tested with Vdd = 3.5V. *** Leakage on I/O pins is typically checked for +/- 10 microamps with the output device turned off and no pull-up or pull-down device present.
2.3 Operational Specifications
Table 6: Operational Specifications Parameter Receiver Frequency range Sensitivity Noise figure IIP2 IIP3 Image rejection Input impedance RSSI gain IIN IDDS Ton TRX_TX/ TTX_RX IF bandwidth LNA Input trim Output trim 1.2 0.32 4 0.91 2 pF pF Internal capacitor range for the receiver input Internal capacitor range for the output of the LNA in the receiver Crystal mode 16 10 12 30 300 -107 -104 6.0 7.8 +60 +5 40 Figure 8 18 12 14 2 150 1500 300 20 14 16 50 960 -114 -111 9.0 MHz dBm dBm dB dBm dBm dB mV/dB mA mA mA us us kHz Receiver current consumption at 900MHz (AMIS-53050-001) Receiver current consumption at 900MHz (AMIS-53050-002) Stand-by mode with crystal oscillator running Stand-by to receive mode transition time Transition time from RX to TX or TX to RX The receiver bandwidth is fixed Dual tone test using RSSI Dual tone test using RSSI Modulated desired, single tone interferer Receiver input impedance with given LNA input/output coils Frequency is set by external VCO components & registers @ 10kHz data rate (FSK/GFSK modulation) @ 10kHz data rate (OOK modulation) Min. Typ. Max . Units Comment
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AMIS-53050 Frequency Agile Transceiver
Table 6: Operational Specifications (Continued) Parameter Min. Typ. Max. Transmitter Frequency range Ton TTX_RX OOK on/off ratio FSK frequency separation CW output power PHARMONICS TX PA Output cap. Output switch R On/Off ratio Output harmonics Operating current Operating current High MAX power power Low power High MAX power power Low power Crystal Oscillator Center frequency Tolerance Startup time Startup time Trim cap Trim resolution Idd Idd 10kHz Oscillator Output frequency Operating current Duty cycle ADC Resolution FSR Ci Reference offset fclk Conversion rate Conversion time 10 0.01 8 2 1 1 2 150 Bits V pF %FSR MHz KSPS Tclk Clock frequency Clock rate = 2MHz Full scale input range Input capacitance 9.8 300 10 375 50 10.2 450 kHz nA % After trimming After trimming 0 145 160 800 1.5 50 2 50 12 12.5 -1 13.8 3 15 4.5 15.5 4 2 5 60 -35 68 24 17 5.7 17 5 7.5 18 pF dB dBc mA mA dBm Matching network for 50 928MHz high (dedicated TX port) dBm dBm Matching network for 50 433MHz high (dedicated TX port) dBm With typical 50 matching circuits 15dBm CW 0dBm CW Internal capacitor range for the PA adjustable trim 300 150 150 60 0 -20 -25 35 200 15 0 960 MHz us us dB kHz dBm dBm dBc Allowable transmit/receive peak deviation Stand-by to transmit mode transition time Transition time from TX to RX
Data Sheet
Units
Comment
Range of output power in the high power mode (dedicated TX port) Range of output power in the low power mode (dedicated TX port) With complete matching network
24 20 150 5 45 175
MHz ppm us ms pF fF uA mA
Trimmed Required crystal tolerance Quick Start enabled Quick Start disabled Internal trim capacitor (Self-calibration sets) Normal operation During Quick Start
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AMIS-53050 Frequency Agile Transceiver
Table 6: Operational Specifications (Continued) Parameter Min. Typ. Max. Data Filter 3dB Down point Temperature Sensor Output voltage Voltage range Slope RSSI Buffer Input range Operating current Unity gain-BW PLL Reference input frequency Resolution 9.62 VCO gain constant Settling time Phase noise Phase noise Max. spurious level POR Delay time Brown-out trip 28 1.2 43 1.6 60 1.8 ms V 25.6 12 16 91.55 12 32 100 -90 -120 -70 -80 -110 -50 14.4 38.4 MHz MHz Hz MHz/V MHz/V us dBc/Hz dBc/Hz dBc Transmit mode (24MHz external crystal) Receive mode (24MHz external crystal) Frequency step size @ 900MHz, although layout PCB @ 400MHz parasitics and component @ 900MHz placement will change this value Internal loop filter Internal loop filter @ 10kHz offset Internal loop filter @ 3MHz offset Internal loop filter 0 135 615 185 1000 Vdd 250 1700 V uA kHz 100k/100pF load 0.93 0.61 0.97 0.97 -5.24 1.01 1.4 V V mv/ C
o
Data Sheet
Units %FDATA
Comment AM data filter bandwidth (relative to associated defined data rates) At 27 C Output dV/dT
o
110
120
130
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
3.0 Block Diagrams
3.1 AMIS-53050 Overall Block Diagram
Figure 1: AMIS-53050 Block Diagram
3.2 Package 3.2.1. Pin Definition
Table 7: Pin Definitions Pin# -001 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LNAvdd RFin RFvss RFout RFpwr Avdd ADC1 ADC2 RSSI PEAK Avss XTAL2 XTAL1 INT Dopt Dssn -002 LNAvdd RFin RFvss RFout RFpwr Avdd ADC1 ADC2 RSSI PEAK Avss XTAL2 XTAL1 INT Dopt Dssn Pin Type Power Analog input Ground Analog output Analog output Power Analog input Analog input Analog IO Analog Ground Analog Analog Digital output Digital input Digital IO Description A DC short (inductor) is connected to VDD from this pin The RF input to the receiver circuits Ground for the RF circuits RF transmit output Variable DC voltage output to power the RF transmitter (requires a DC short {inductor} connection to RFout) Vdd power for the analog circuits Input to the analog to digital conversion circuit Input to the analog to digital conversion circuit Analog voltage related to the strength of the received RF Analog voltage for external auto-slice capacitor Ground for the analog circuits Connection to an external crystal Connection to an external crystal Interrupt to external controller Optional data pin for the 4-wire data interface mode Active low select line for the data interface
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AMIS-53050 Frequency Agile Transceiver
Table 7: Pin Definitions (Continued) Pin# -001 -002 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Drxtx Dclk SYSclk Dvss Dvdd CoreReg SCLK SDATA xBURST LOOPout LOOPin LOvss LOn LOp LOvdd RFvdd Drxtx Dclk SYSclk Dvss Dvdd SSN SCLK SDATA xBURST LOOPout LOOPin LOvss LOn LOp LOvdd RFvdd
Data Sheet
Pin Type Digital IO Digital IO Digital output Ground Power Digital Digital Digital Digital input Analog Analog Ground Analog Analog Power Power
Description Serial data input (Transmit) or output (Receive) Recovered clock output (Data interface clock) System clock output Ground for the digital circuits Vdd supply for the digital circuits -001 (pin bonded for a decoupling capacitor for the internal regulator) -002 (pin is bonded to bring out the SSN bus enable for the control bus) Bi-directional clock for the 2-wire serial interface Bi-directional data for the 2-wire serial interface Active low input interrupt that will immediately cause a Burst transmission Output to the optional external loop filter Input from the optional external loop filter Ground for the local oscillator circuits Negative side of the VCO tank Positive side of the VCO tank Vdd supply for the local oscillator circuits Vdd supply for the RF circuits
3.2.2. Block Diagram/Pin Definition
Figure 2: Block Diagram/Pin Definition *
* Not actual package markings. Please see marking format in 3.2.3.3.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
3.2.3. Physical Characteristics
3.2.3.1. Package Type
32 pin LQFP
3.2.3.2.
Package Dimensions
Table 8: AMIS-53050 LQFP Package Dimensions Symbol Min. Nom. Max. Units Thickness D D1 E E1 e 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.80 BSC 1.60 mm mm mm mm mm mm
Figure 3: Package
3.2.3.3.
Package Marking Format
(AMIS Logo) AMIS53050 19608-bbb XXXXYZZ Where: bbb is the AMIS device version XXXXYZZ is the date and tractability code**** is the country of origin (found on underside of chip). The year in which the mask work was first fixed in a semiconductor chip product may also appear.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
4.0 Acronyms
The following acronyms are used in this document. ADPLL AM ASIC ASK ASSP ASTRIC CCA CDR CRC CW DAC dB dBm DFFT DPLL EE FFT FM FSK GFSK IF kbps kHz LO LOP MHz mV OOK OTA PLL POR RF RSSI SOF VCO All digital phase lock loop Amplitude modulated signal (AM/ASK/OOK are used interchangeably in this document) Integrated circuit designed for a single customer requirement Amplitude shift key (AM/ASK/OOK are used interchangeably in this document) A custom integrated circuit, that may be used in general designs AMI Semiconductor's family of wireless products Clear channel assessment Clock and data recovery, data is recovered from the received signal using a synchronous clock Cyclic redundancy checking; data error checking Continuous wave, a single frequency or modulated signal carrier Digital to analog conversion Decibels; a logarithmic measure of signal level Logarithmic measure of signal level above a milli-watt Digital or discrete Fast Fourier transform (DFFT/DFT/FFT may be used in this document and mean the same) Digital phase locked loop circuit to create a precise frequency Electrical erasable memory that can maintain data with power removed Fast Fourier transform; transform between time and frequency (DFFT/DFT/FFT may be used in this document and mean the same) Frequency modulated signal (FM/FSK are used interchangeably in this document) Frequency shift key (FM/FSK are used interchangeably in this document) Gaussian data waveform modulated signal Intermediate frequency Data rate in thousand bits per second Frequency in kilohertz per second Local oscillator frequency; used to convert signals between RF frequency and IF frequency Byte indicating the length of a packet Frequency in megahertz Milli-volts On/off method of creating an amplitude modulated signal (AM/ASK/OOK are used interchangeably in this document) Transconductance amplifier Phase locked loop circuit to create a precise frequency Power-on-reset is a threshold circuit for limiting operation at low voltages Radio frequency Received signal strength Indication; measurement of RF signal strength Byte indicating start of packet in data protocol Voltage controlled variable frequency oscillator
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AMIS-53050 Frequency Agile Transceiver
5.0 Hardware Description
5.1 Frequency
Data Sheet
The RF frequency for both TX and RX modes is determined by the combination of internal VCO, PLL and trim capacitors, as well as an external crystal oscillator. For the external crystal, it is recommended that a 24MHz parallel resonant mode crystal with 20ppm tolerance be used, taking into account the internal capacitors.
Figure 4: External Crystal Circuit
The internal VCO requires an external, parallel LC configuration in order to properly set the frequency for RX or TX modes. Operation of the AMIS-53050 is sensitive to the positioning of the LC components in the PCB layout. For this reason, the traces to the LC need to be as symmetrical as is possible. The location of the LC components needs to be as close as possible to the transceiver pins as well. Any layout changes will lead to a change in the VCO frequency, in turn requiring a change in the values of the inductor, capacitor and/or the values in the register(s) controlling the RF frequency. The layout of the printed circuit board for the inductor and capacitor should route
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
traces connecting other components away from the inductor and capacitor pads. Furthermore, the values of the inductor and/or the capacitor are to be optimized in order to properly calibrate the PLL for a given frequency of operation. The AMIS-53050 has an internal loop filter which is linked to the PLL circuit to generate the transceiver's output frequency. There is an option to use an external loop filter.
Note: Using a capacitor in parallel with an inductor for the external VCO LC circuit will lower the VCO gain, reducing the frequency overlap between the transmit frequency and the receive frequency. It is suggested that only a coil be used in the LC circuit, if possible. Note: The PCB traces to the external LC components need to be as symmetrical as possible. Note: The external L and C used to set the VCO frequency should be physically located as close to the AMIS-53050 Pins LOp, LOn as possible.
Figure 5: VCO External LC Circuit
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AMIS-53050 Frequency Agile Transceiver
Table 9: Internal Loop Parameters Filter Component R1 Second order C1 C2 Additional pole Reference VCO gain CP current R C Frequency N KVCO KVCO ICP ICP 22 10 25 50 MHz/V MHz/V Value 60 64 3 110 1 24 Units k pF pF k pF MHz N=(RF MHz)/(24 MHz) VCO external coil inductance ~ 15 nH VCO external coil inductance ~ 91 nH The charge pump current is user selectable The charge pump current is user selectable Comments
Data Sheet
A A
Figure 6: Optional External Loop Filter Circuit
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
In the low power mode (idle/stand-by), an internal 10kHz oscillator provides timing for the sniff, burst transmit and housekeeping functions, respectively. This oscillator requires no external components. The 10kHz oscillator's internal trim capacitor is trimmed by eight bits of trim control via self-calibration. Once the trim is set, the oscillator frequency will be accurate to within two percent over specified voltages and temperatures. 5.2 Receiver The AMIS-53050 has a single channel receiver. The LNA for the receiver input requires a DC connection to ground on the input (must not be an RF ground connection). The LNA for the receiver input requires a DC connection to RFVDD on the output. These connections are supplied through inductors, Lrx and LLNA, becoming part of the matching circuit for the receiver input.
Figure 7: Receiver Input Matching Circuit
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AMIS-53050 Frequency Agile Transceiver
5.2.1. Receiver Low Noise Amplifier (LNA)
Data Sheet
The receiver input of the AMIS-53050 is a single-ended input and single-ended output device. The input is matched to 50 using an external matching network, which provides a DC path to ground for biasing the receiver's LNA. The output of the LNA is tuned to the desired operating frequency using an external inductor along with an on-chip capacitor. The output inductor also provides the LNA with a DC connection to the supply voltage. On-chip tuning capacitors are binary weighted and digitally controlled. The value of the internal input capacitance has a range of 1.2 - 4pF. The corresponding range for the internal output capacitance is 0.3 - 0.9pF. The impedance of the receiver for three values of input coil inductance, with the input capacitance set to the middle of the range (register set to 0X80), is shown in Figure 8. Here, the value of the output coil inductance is a function of the operating frequency, and is shown in Figure 9.
Figure 8: RX Input Impedance
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 9: Receiver LNA Output Inductor Selection
5.2.2. IF Filter A passive poly-phase filter and active filtering are used to achieve frequency selectivity and rejection of the image frequency. The filter is designed to provide an optimal image rejection of 50dB at 500kHz below the RF frequency.
5.2.3. Data Filter The OOK low-pass data filter is used for additional post-detection signal filtering in accordance with the OOK signal data rate (1.2, 1.8, 2.4, 4.8, 7.2, 9.6, 14.4, 19.2kHz).
5.3 Transmitter The transmitter is a two-stage output amplifier. When both stages are selected, the highest output power at frequencies from 300MHz to 960MHz is +15dBm, when matched into a 50 load. For output power levels up to 0dBm, single stage operation results in higher power efficiency, as compared to two stage operation. The voltage output level on the RFPWR pin controls the RF output power level of the device. A DC connection must be made between the RFOUT pin and the RFPWR pin. The non-linear output of the AMIS-53050 may require external components to match to a load and to reduce the spurious harmonics. The output impedance of the AMIS-53050 can be matched to the impedance of an external load, using the spreadsheet AMIS53RFMATCH.xls. This spreadsheet is provided by AMIS and is described in the Application Note "AMIS-53XXX Antenna Impedance Matching Considerations".
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 10: Transmitter Output Matching Circuit
5.4 Single Antenna Option The AMIS-53050 is designed such that when the transmitter or the receiver is off, the respective pin is grounded. This provides a known impedance for the off port (transmit or receive), in order to allow the use of a single circuit topology combining the receiver and the transmitter into a single antenna. In the AMIS-53050, a single register is used to set the transmit and receive frequency, resulting in the same transmit and receive frequency. Therefore, the simple method to combine the transmitter and the receiver into a single antenna will lead to either a reduction in transmit output power or less sensitivity in the receiver.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Note: This section offers a simple method to combine the transmitter and the receiver into a single antenna. The AMIS-53050 turns the receiver off and shorts the input to ground so that any transmit energy will not affect the receiver circuits. Combining the transmitter and receiver is typically done in one of two ways: 1. A diplexer can be used if the transmit and receive frequencies are different and far enough apart to allow bandpass filtering to separate the signals. Typical diplexers have less than one dB path loss. 2. A T/R (transmit/receive) switch can be used when the transmitter and the receiver are at the same frequency. Typical T/R switches have 1 to 1.5 dB path loss and require a signal to control the direction of the switch. The AMIS-53050 is not designed to provide a T/R switch control signal.
Figure 11: Single Antenna Port T/R Matching Circuit
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AMIS-53050 Frequency Agile Transceiver
5.5 Peak
Data Sheet
There are three methods for slicing the received OOK modulated signal to recover the data. The first method is based on setting a threshold value that is fixed and to which the receiver compares the recovered signal. The other two methods are based on automatic setting of this threshold level. These automatic threshold methods require an external capacitor on the PEAK pin to operate. Please refer to the Application Note "Setting up the Data Slicing Modes" for information on proper selection of the capacitor values. In the averaging method, the transceiver's low pass filter circuitry is enabled, with a cut-off frequency set below the data rate filter setting. This filter extracts an average RSSI level as the data slice threshold. The time constant (corner frequency) for this filter is in turn determined by the value of the capacitor connected to the PEAK pin. A typical capacitor value would allow the average level to settle to 95 percent of the RSSI level in 2 bit intervals (remember that Manchester encoding may have transitions twice the data rate). The average threshold method will have chatter before a signal is received and after the signal ends, which should be considered for proper operation of the external host controller. In the peak method, the peak detector circuitry is enabled, followed by detection of the maximum input signal level and setting of the threshold level 6dB lower than the maximum level, respectively. The capacitor connected to the PEAK pin is used to bleed or discharge -3 the peak voltage in the circuit. The voltage swing on the RSSI for a typical 12dB signal to noise ratio at 10 BER is 240mV. The capacitor value should not change the voltage by more than this 240mV during a string of zeros. The value is dependent on the number of zeros that are allowed in the chosen data protocol, NRZ or Manchester encoded. In the AMIS-53050, the sniff function can be used to adjust the threshold energy level in order to accommodate changes in the external noise floor and/or the gain of the receiver due to temperature and voltage. This is done by setting a false wake-up value (number of false wake-ups during a given number of sniff events).
Figure 12: Peak Capacitance Circuit
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AMIS-53050 Frequency Agile Transceiver
5.6 ADC
Data Sheet
The ADC is a successive approximation analog to digital converter, using an internal 8-bit DAC as the reference. The ADC data for the selected input channel(s) will be stored in the associated register, allowing for external access to the conversion data through the serial interface. Commands in the control register allow for single or continuous operation of the ADC. The ADC results can also be read and automatically transmitted to another device using the burst transmit mode. A voltage regulator generates the 2.0V reference for the ADC and DAC based upon an internal bandgap voltage source. The ADC has six inputs, two of which are available for use in the designer's application.
5.7 Control Interface Serial Bus The internal registers of AMIS-53050 can be accessed via a 3-wire (requires the -002 version of the AMIS-53050) or 2-wire I2C interface, respectively. In this case, the states of the three lines, SDATA, SCLK and SSN, and hence the type of interface are automatically detected and configured by the transceiver's control logic. This configuration will be valid as long as power is not removed or a reset function is not initiated.
2 2 2 I C: If SSN is high and an I C start bit is detected, I C mode is enabled
SPI: If SSN is low, and a negative edge on SCLK detected, SPI mode is enabled The AMIS-53050 is designed to conform to the Philip Semiconductor I2C standard, with the AMIS-53050 as the slave device.
Figure 13: I2C Serial Bus Connections
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 14: 3-Wire Control Bus Connections
5.8 TX/RX Data Interface Serial Bus Data transfer between AMIS-53050 and the external host controller is based on a 3-wire or 4-wire SPI serial data interface, respectively. The interface type is selected by writing to the appropriate register. The DOPT line is undefined in the 3-wire interface. The 4-wire interface of the AMIS-53050 is designed to be compatible with the definition of a standard SPI interface. The device can be configured as a master or a slave. The state of the device (master or slave) and the interface mode (read or write) will determine the definition of the DRXTX and DOPT pins as outputs or inputs, respectively.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 15: SPI Compatible Serial Data Interface
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 16: 3-Wire Serial Data Interface
5.9 System Clock The system clock can be used as a clock for the external host controller. The clock frequency can be divided down from the 24MHz crystal frequency. In this case, the system clock can be output according to the following conditions: * * Will be output in RX or TX, unless the output is off in general options B (Bit 1:0) The output will start back up in the idle mode after a packet is received
The output will start back up in the housekeeping mode if wake-up external host controller is enabled in the housekeeping configuration (Bit 6). Note: The SYSclk produces harmonics, which may land within the AMIS-53050 receiver frequency and may reduce the sensitivity of the receiver. th * For example, the 30 harmonic of a 12MHz SYSclk is 360MHz and would affect receiver sensitivity of a system designed for 360MHz operation. * A suggestion is to disable the SYSclk output in applications not using this feature of the AMIS-53050. * The PCB layout of an application, which uses the SYSclk must use good isolation techniques for reducing the noise from the SYSclk output in the AMIS-53050 receiver.
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AMIS-53050 Frequency Agile Transceiver
Table 10: System Clock Control Mode Control CLKout pin Standby Idle 0X0D General options B General options A Idle config Bits 1:0 2:1 0 4:3 Outputs Frequency: 12, 6, 3MHz or off POR state: standby, idle, RX, TX Output in standby Clock cycles before stop Comments
Data Sheet
5.10 Power and Grounds The AMIS-53050 has four distinct supply voltage inputs and two different ground nodes, respectively. This allows the separation of the RF, analog and digital power supply circuits to reduced coupled noise in these circuits.. The same principle applies to the ground nodes, where a separate ground plane can reduce the amount of noise induced into the sensitive RF circuits.
5.11 Design Suggestions The following schematics and board layouts depict typical board-level solutions for the AMIS-53050:
Figure 17: Typical Design Schematic
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 18: Typical Design Layout Suggestion
Figure 19: Minimum Design Schematic
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 20: Minimum Design Layout Suggestion
6.0 User's Guide
This user's guide divides the description of the control registers into distinct functional areas; command register flow diagrams, frequency generation, receiver, transmitter, idle, data/control interfaces, and burst transmission, respectively. 6.1 Control Serial Interface Bus Description
Table 11: Control Interface Physical Configuration Interface AMIS53050 Version -001 -002 -002
2
Clock Pin SCLK SCLK SCLK Source Master Master Master
Data Output SDATA SDATA SDATA Input SDATA SDATA SDATA SSN RegC NU Select AMIS-53050 Slave only Slave only Slave only RX Low Med. Med.
Power Standby Med. Low Low
IC 3-Wire
2
Note: The I C control bus interface can be used with either the -001 or the -002 version of the AMIS-53050, but the SPI can only be used with the -002 version. The versions are different due to the receiver power requirements as shown.
The AMIS-53050 employs two different control interfaces. Communication with the AMIS-53050 control registers is through either a 3-wire bus or a 2-wire I2C compatible bus, respectively. The state of the control bus is detected by the device at the onset of communication with the host controller, and is valid as long as power remains applied to the part. In this case, the transceiver is always a slave device.
6.1.1. Control Interface Protocol The AMIS-53050 control interface allows an external host controller to write instructions to the registers. The external controller can also read the register values. The control interface can be configured as either a 2-wire I2C interface bus or a 3-wire serial interface (slave mode operation).
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
The 3-wire interface allows a single host controller to address more than one transceiver using the single serial interface bus (requires a different SSN control line for each device). However, note that the 3-wire interface has only six register address bits and cannot address the entire register space.
2 2 The I C interface requires a single host controller for each transceiver. The I C interface allows the AMIS-53050 bonding option defining the SSN/CoreReg pin as the external capacitor required for the low power digital regulator. The digital regulator reduces the receiver power consumption.
Figure 21: Control I2C Protocol Format
Table 12: I C Addressing Address 0110100X 01101000 01101001
2
Description AMIS-53050 I C address AMIS-53050 Write command AMIS-53050 Read command
2
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 22: 3-Wire Control Protocol Format
Table 13: 3-Wire Control (IN1 and IN0) Control Word Bits Description IN1 IN0 0 0 1 1 0 1 0 1 Single register read Single register write Sequential register read Sequential register write
I2C device address: o 0x68 HEX for device write o 0x69 HEX for device read External controller can write registers External controller can read registers External controller can issue a immediate transmit via the xBURST input External controller can receive an interrupt (xINT) from the AMIS-53050 Set-up registers descriptions: I2C/3-wire select- First write to the interface sets the type of interface until AMIS-53050 is power cycled
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AMIS-53050 Frequency Agile Transceiver
6.1.2. Serial Control Interface: Configuration
Data Sheet
The AMIS-53050's control logic can automatically detect the type of interface used for the serial control bus. The interface pins are then given the definitions as shown in Table 14. The detection scheme is based on the status of the device pins, as shown in Figure 23.
Table 14: Control Port Pin Definitions Pin Name SCLK SDATA SSN I2C Mode SCL SDA Internal pull up 3-Wire Mode SCLK R/W controlled SSN
Figure 23: Control Interface Selection
Addressing the part with the desired protocol will result in the configuration of the interface settings. After the first communication with the device, the selection is locked until power is removed. The internal logic for determining which protocol to use on initial power-up is as follows:
2 2 2 I C: If SSN is high and an I C start bit is detected, I C mode is enabled. 3-wire: If SSN is low, and a negative edge on SCLK detected, 3-wire mode is enabled. 2 The internal pull-ups on SCLK and SDATA can also be disabled for I C applications using external pull-ups.
Table 15: Control Interface Pull Up Control Mode SCLK, SDATA Pull Ups Controlled by bit 3 of the general 2 IC options A register Controlled by bit 3 of the general 3-wire options A register
SSN Pin Configuration Not used (internal pull up) SSN: normal mode
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
6.1.3. 3-Wire Interface Mode The AMIS-53050 is always the slave device.
Figure 24: Master/Slave for Bi-Directional 3-Wire Mode
Figure 24 illustrates the connections between the master SPI port and the slave 3-wire port in the AMIS-53050.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 25: Single Control Register Read/Write Using the 3-Wire Interface
Figure 25 shows a single read or single write control data transfer. The operation starts with SSN transitioning low to indicate a start of transfer. The first two bits transferred are the instruction for the slave interface of the AMIS-53050, namely IN1 and IN0, respectively. Following the instruction are the six address bits to specify which address to read or write. If the instruction is to write to a register, the register location is A<5:0> and the data is specified with the next eight bits, D<7:0>. If the operation is a read function, the slave output buffer is enabled at the end of the address bits, and the data bits D<7:0> are buffered out of the part MSB first. For single read/write, the SSN line can remain active between successive read and write operations.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 26: Sequential Control Register Read/Write Using the 3-Wire Interface
Figure 26 is a diagram for sequential reads or writes for 3-wire control data transfer. The format of the instruction and address is identical to that for a single read/write operation, with the address corresponding to the first register location to read or write. The first eight bits of data transferred correspond to the address selected. The address is internally incremented after each data byte is transferred. This task is most useful for writing to or reading from variables spanning over multiple address locations, such as the fractional PLL word (registers 03-05). The SSN line must be de-asserted at the completion of a sequential read/write in order for the slave SPI controller to correctly interpret the next eight bits as a command and not data.
2 6.1.4. I C Interface 2 2 The I C interface for the AMIS-53050 is compatible with the Philip Semiconductor I C standard, with the AMIS-53050 as the slave device.
6.1.4.1.
I2C Device Addressing
A control byte is the first byte received following the start condition from the Master device. The control byte consists of 7-bits for the device address, and 1-bit for a read or write command. For the AMIS-53050, the device address is `0110100' binary. The last bit of the control byte defines the operation to be performed. When set to `1', a read operation is selected. When set to `0', a write operation is selected. Following the start condition, the AMIS-53050 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving its device address, the AMIS-53050 outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the AMIS-53050 will select a read or write operation.
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AMIS-53050 Frequency Agile Transceiver
6.1.4.2. Single Register Write
Data Sheet
Figure 27: Single Control Data Read/Write with the I2C Interface
The master device issues the start condition, then issues the device address, and then issues the single R/W bit, a logic low state. This indicates to the addressed slave receiver that a byte with a register address will follow after the slave has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the register address to be written with data. After receiving another acknowledge signal from the AMIS-53050, the master device will transmit the data word to be written, and the AMIS-53050 will acknowledge again. The write cycle ends with the master generating a stop condition. A similar approach is used to read a register value. The Master device issues the start condition, then issues the device address and then issues the single R/W bit, a logic low state. This indicates to the addressed slave receiver that a byte with a register address will follow after the slave has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the register address to be read. After receiving another acknowledge signal from the AMIS-53050, the master device will immediately follow with another start sequence, however, the R/W bit is now set high, telling the slave device that the master wants the contents of the register (addressed with the write command) to be placed on the SDA bus line. After the Master reads the eight bits of data, the master does not acknowledge but sends the stop sequence.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
6.1.4.3.
Sequential Register Write
Figure 28: Sequential Control Data Read/Write with the I2C Interface
When setting up the AMIS-53050 for an application, it is sometimes desirable to write the data to a number of registers sequentially. The write control byte, register address and first data byte are transmitted to the AMIS-53050 in the same way as in a byte write. However, instead of generating a stop condition, the master can continue to write register locations. Upon receipt of each word, the address is internally incremented by `1'. Should the master transmit more words than the AMIS-53050 has address locations, the address will roll over to the first address. Reading a register value is based on a similar approach. The write control byte and register address are transmitted to the AMIS-53050 in the same way as in a byte write. After receiving another acknowledge signal from the AMIS-53050, the master device will immediately follow with another start sequence, however, the R/W bit is now set high telling the slave device that the master wants the contents of the register (addressed with the write command) to be placed on the SDA bus line. After the eight bits are read by the master, the master acknowledges the reception. The AMIS-53050 will increment the register address and continue to output register values. After the last register value is received by the master, the master does not respond with an acknowledgement but sends the stop sequence.
6.1.4.4.
Current Address Read
The internal address counter maintains the last address addressed, incremented by `1'. If the last instruction received was to access register N, the current address read operation will read the contents from register N+1. The timing for the current address read is to send a start bit followed by the 7-bit device address, with the R/W bit set to one. The slave will acknowledge, after which the 8-bit register contents will be transmitted. The master does not acknowledge the transmission, but does generate a stop bit.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
6.1.4.5.
Interface Options
2
Table 16: I C Address Auto Increment Register Number (HEX) 0X0C 0X47 Name General options A Analog test mode Bits 3 4
Function Disable the internal pull up resistors on SDATA and SSN lines I C Auto increment disable*
2
*Note:
To write to this register, the test registers must be unlocked by writing a special code to the UNLOCK KEY register (0X40).
6.1.4.6.
Pull- Up Disable
The AMIS-53050 includes built in pull-up resistors for use with the I2C operation, in order to reduce the overall system component count. The pull ups are asserted at POR until mode selection occurs. If the mode is determined to be 3-wire, the pull-up resistors are 2 removed. If the mode is determined to be I C, this option bit determines whether the pull-up resistors are to be removed.
6.2 Command Register The AMIS-53050 provides for single writes to an on-chip 8-bit register, in order to select different operating modes. It is very important to note that all registers associated with the desired mode are to be pre-programmed, for the single write to this register to operate correctly. The command register allows for the user application to issue a single write command to the device, in order to initiate the functions listed in Table 17. Once a function is initiated, the AMIS-53050 uses the register values associated with the selected function to perform the desired operation(s). These register values will be the default values or the values the user application has written to the registers before the function is called out in the command register. Most of the register values can be stored in the integrated EE memory so that the transceiver can be powered up in the desired configuration.
Table 17: Command - 0X00 [0] Bit Command [7:4] [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1111 [5:0] XXXXXX 100000 XXXXXX 100000 Stand-by Receive Transmit Idle Idle Return Write EE Read EE Calibrate QS Osc Calibrate RC Calibrate PLL Calibrate LNA ROM2Regs Global Reset Single ADC Conversion Continuous ADC Conversions
Comment Put the part into stand-by Put the part into receive mode Put the part into transmit mode Put the part into idle mode Use to return to idle after interrupt for HK or receive during sniff Write the content of the working registers into EE Read the contents of the EE Calibrates the Quick Start oscillator Calibrates the 10kHz RC oscillator Calibrates the PLL Calibrates the LNA matching Write the content of the ROM into the shadow registers Resets the part completely Do an ADC one time on the channel selected loop filter output Do an ADC on the channel selected continuously loop filter output
0000
[7:6] 01 11
With reference to Table 17, stand-by mode can be classified as either a low power mode (where all internal circuitry except for the control bus interface are disabled), or a clock-only mode (where the crystal oscillator will be enabled to continue providing a system clock for an external microprocessor). A bit available in the general options A register allows for selection of power-down or clock-only operation. Many of the instructions are finite in duration. In this case, the AMIS-53050 will return to the stand-by mode at the completion of the task. Other instructions such as receive or transmit are indefinite in length and user-controlled, hence to return to the stand-by state, the transceiver waits for the stand-by instruction.
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AMIS-53050 Frequency Agile Transceiver
Note that there are two low-power modes for the AMIS-53050; stand-by and idle. Stand-by allows the SYSCLK output Idle is the very low power state without SYSCLK output (allows for housekeeping, sniff or burst functions)
Data Sheet
The device's control logic may ignore a new instruction if it is busy or if it is not ready to receive the instruction. For example if a selfcalibration is in process and the transceiver is to transmit or receive a message, the instruction may be ignored. It is recommended that the host controller is configured to monitor the transceiver's status registers listed below prior to issuing a new instruction: Busy Instruction Enable Status/Flag Register 2 bit 0 indicates that the AMIS-53050 is still performing a task Status/Flag Register 1 bit 1 indicates that the AMIS-53050 is ready to receive a new instruction
Note: Instructions issued to the command register may be ignored by the AMIS-53050 if it is busy (busy status bit) or it if is not ready to receive a new instruction (instruction enable status bit). An application program should poll these status flags.
6.3 Functional Flow Diagrams
Figure 29a: Receiver Flow Diagram
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 29b: Receiver Flow Diagram (cont.)
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 30: Transmitter Flow Diagram
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 31: ROM 2 Regs
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 32: Idle State Flow Diagram
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 33: EE Flow Diagram
6.4 Frequency The AMIS-53050 uses an internal PLL/VCO to generate the RF frequency for both transmit and receive modes of operation. Only one set of registers needs to be programmed to generate the TX frequency and to generate the LO frequency to produce the mixing frequency for converting the received signal to the low IF (about 500kHz). The self-calibration process will in turn trim internal capacitance to tune the TX and RX frequencies. The self-calibration process is to be executed at least once following start-up or after a significant change in the RF frequency. The on-chip processor will calculate four (300kHz) channels above and four (300kHz) channels below the center frequency entered into registers 0X05, 0X06, 0X07 and 0X08, respectively. This occurs once a ROM2REGS instruction is executed. Caution is advised when using any of the multi-channel features of the device, as the operating frequency could be altered.
6.4.1. Frequency Control AMIS has developed an executable program (AMIS-53KFractNCalc.exe), available from AMIS, which generates the register values for the frequency divider and 24-bit fractional word to produce a desired frequency. First, the AMIS-53050 must have the correct LC for the
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
desired frequency connected to the VCO pins. There is internal capacitance, which is part of the capacitance for determining the value of the inductor. The following equation can be used to determine the approximate value of the LC components. Please note that the VCO is sensitive to the placement of the LC components. The components should be placed as close to the AMIS-53050 as practically possible (even short traces add significant parasitics) and the traces to the components should be made symmetrical. The VCO in the AMIS-53050 is a differential negative resistance oscillator (DNRO), commonly found in the literature. It uses an internal voltage variable capacitor (varactor) in combination with an external L and C to provide the desired frequency. The output frequency is estimated by:
Where: Ltot and Ctot are the total inductance and capacitance respectively at the VCO pins. This includes the internal capacitance of approximately 2pF. The RF PLL is a 24-bit sigma delta based fractional N synthesizer used to provide the LO signal for receive, and alternately a direct RF output for transmit. Register descriptions: RF Divider- The RF frequency of the receiver must be configured. This is done in two steps; the first and second steps pertain to setting the RF divider and setting the fractional N word, respectively (AMI Semiconductor has produced a program for determining the values for these registers, AMIS53KfractionalNCalculator) RF Frequency- Program the three register fractional N word (AMI Semiconductor has produced a program for determining the values for these registers, AMIS53KfractionalNCalculator) Peak Deviation- When the data modulation is to be FSK, the two register peak deviation must also be set. The deviation should be set to a value between one half and one times the data rate. Maximum deviation is about 200kHz for any data rate.
6.4.1.1.
RF Divider
Setting the RF channel frequency is done through the RF divider register, along with the RF frequency 2, 1 and 0 registers. The RF divider register is used to specify the integer portion of the divide value, and the RF Frequency 2, 1 and 0 registers are used to specify the fraction. The values are calculated as follows:
Where FChannel is the desired RF center frequency. The value for the RF divider register is found by,
Where integer is the value used for RF divider. The last step is to calculate the fractional value. This is done as,
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Fraction is the value to be used in the RF frequency 2, 1 and 0 registers. As an example, if the desired RF frequency channel is 903.5MHz,
For this example, the RF divider register is written to 0x26, RF Frequency 2 is written to 0xFE, RF Frequency 1 to 0x95, and RF Frequency 0 to 0x54.This value +/- 1 is fed directly to the PLL as N0 and N1. (i.e. if 63, send 64 and 65 to the PLL)
Table 18: RF Divider - 0X05 [5] Bit Name 7:0 RF_divide [7:0]
Comment
The divider value is the rounded result of dividing the RF frequency by 24MHz
6.4.1.2.
RF Frequency 2
Table 19: RF Frequency 2 = 0X06 [6] Bit Name Comment 7:0 RF_FREQ [23:16] Upper 8 bits of the RF fraction
6.4.1.3.
RF Frequency 1
Table 20: RF Frequency 1 - 0X07 [7] Bit Name Comment 7:0 RF_FREQ [15:8] Center 8 bits of the RF fraction
6.4.1.4.
RF Frequency 0
Table 21: RF Frequency 0 - 0X08 [8] Bit Name Comment 7:0 RF_FREQ [7:0] Lower 8 bits of the RF fraction
6.4.1.5.
Peak Deviation 1
The peak deviation for FSK transmissions is determined by the peak deviation 1 register and the peak deviation 0 register. This value is also used inside the DFT FSK detector. Calculation of the value for the peak deviation is straightforward:
The result of this equation, converted to Hex, is entered into the peak deviation registers.
Table 22: Peak Deviation 1 - 0X09 [9] Bit Name Comment 7:0 PEAK_DEV [15:8] Upper 8 bits of the peak deviation
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AMIS-53050 Frequency Agile Transceiver
6.4.1.6. Peak Deviation 0
Data Sheet
Table 23: Peak Deviation 0 - 0X0A [10] Bit Name Comment 7:0 PEAK_DEV [7:0] Lower 8 bits of the peak deviation
6.4.1.7.
RF PLL Options
Contains general options for the setup of the RF PLL.
Table 24: RF PLL Options - 0X28 [40] Bit Name 7 6 5 4 3 2 Kicker calibration status Temperature compensation curve Reserved Reserved Internal loop filter Charge pump current 1 0 1 0 11 01 10 00 50uA 25uA Ivco= 1.2mA Ivco= 800uA Ivco= 600uA Ivco= auto level control Enable using the internal loop filter for the PLL (used for calibration)
State 1 0 1 0
Comment The kicker has been calibrated The kicker has not been calibrated Use the Type 1 compensation for external crystal with curves similar to Type 1 Use the Type 2 compensation for external crystal with curves similar to Type 2
1
Ivco[1:0]
Figure 34: Typical Crystal Temperature Curve for Crystal with Type 1 Characteristics
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 35: Typical Crystal Temperature Curve for Crystal with Type 2 Characteristics
6.4.2. 10kHz Oscillator The AMIS-53050 has an internal 10kHz oscillator which is active in stand-by or idle modes. This very low power oscillator provides the clock for timing functions such as sniff receive, burst transmit or housekeeping. The oscillator is trimmed in the calibration instructions. Register descriptions: 10k Oscillator Trim- The value of the calibration for the 10kHz oscillator. (See Section 6.10.1.4)**
6.4.3. System Clock The AMIS-53050 provides a divided version of the external reference oscillator (typically 24MHz) as an output to an external host controller or other circuits needing a clock.
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AMIS-53050 Frequency Agile Transceiver
Table 25: System Clock Control Register Number (HEX) Name Bits
Data Sheet
Function 11 POR starts in TX
0X0C
General options A
2,1
10 POR starts in RX 01 POR starts in idle 00 POR starts in standby Standby mode with system clock output 11 External XTAL reference divided by 2 (12MHz) 10 External XTAL reference divided by 4 (6MHz) 01 External XTAL reference divided by 8 (3MHz) 00 System clock off 11 System clock continues for 1024 clock cycles 10 System clock continues for 512 clock cycles 01 System clock continues for 256 clock cycles 00 System clock shuts down after idle command ASAP
0
0X0D
General options B
1,0
0X10
Idle config
4,3
Register descriptions: Crystal Oscillator Trim- The value of the calibration for the 10kHz oscillator. (See Section 6.10.1.1)
6.4.4. Quick Start The AMIS-53050 includes the ASTRIC family patented Quick Start oscillator. This circuit uses a "kicker" to force the crystal oscillator close to the final desired frequency. This reduces the time required for the crystal oscillator to settle to the RF frequency. Information on the Quick Start circuit can be obtained in the following documents: QuickStart.doc, and AMIS-53XXX_QuickStartAppNote.pdf.
Table 26: Kicker Calibration Register Number (HEX) 0X28 Name RF PLL Options Bits 7
Function Kicker calibration status
Register descriptions: Quick Start Trim- The value of the calibration for the kicker. (See Section 6.10.1.3)
6.4.5. Self Calibration The AMIS-53050 has internal trim functions for the PLL, TX PLL, RX PLL, 10kHz oscillator, and kicker (Quick Start). A self calibration is started by writing an instruction to the command register. This self calibration needs to be done at least once after the AMIS-53050 has been powered on and before the AMIS-53050 is placed into any mode such as transmit or receive. In this case, the application should monitor the status registers and trim value registers to determine that the calibration was successful. Note: The frequency of the AMIS-53050 can change a small amount (possibly as much as +/- 10MHz at 915MHz) without requiring a new PLL calibration. This tolerance depends on the frequency and VCO coil, so would have to be empirically determined for an application. Note: An RF signal input to the receiver is required when performing the LNA calibration, therefore this calibration is not typically performed. An application designed with the AMIS-53050 should consider the proper way to do an LNA calibration or even if an LNA calibration is needed.
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AMIS-53050 Frequency Agile Transceiver
Table 27: Self Calibration Command Register Number (HEX) Name Code 0X07 0X00 Command 0X08 0X09 0X0A 0X1B Housekeeping config Bit 2 Bit 1 Bit 0
Data Sheet
Function Calibrate the Quick Start (kicker) Calibrate the 10kHz oscillator Calibrate the PLL Calibrate the LNA Calibrate PLL during HK Calibrate 10kHz oscillator during HK Calibrate kicker during HK
Register descriptions: Status- Contains the results of calibrations, instructions and activity in the AMIS-53050. Software State- Shows the current mode of the AMIS-53050. Instruction Enable- Indicates that the AMIS-53050 is ready to receive a new instruction. Busy- Indicates that the AMIS-53050 is still busy with internal tasks.
6.4.5.1.
Status/Flag1
The purpose of the Status1 register is to provide information back to the host on the status of the part. This register should be queried at the completion of calibration sequences to ensure proper operation. The flags will be reset when the register is read. CheckSum indicates whether an attempt to read or write the EE has failed due to an incorrect CheckSum. Instruction Enable indicates that the AMIS-53050 is ready to receive an instruction. This can be used to insure that the AMIS-53050 does not miss a command instruction due to the AMIS-53050 not being ready. Along with the busy flag, these status flags can police the flow of commands to the AMIS-53050.
Table 28: Status/Flag1 - 0X01 [1] Bit Name State 7 6 5 4 3 2 1 0 PLL xLock TX PLL cal RX PLL cal RC cal Quick Start cal CheckSum Instruction enable ADC done 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ADC conversion complete The AMIS-53050 is in a state of operation that can accept instructions EE CheckSum failed Quick Start calibration failed 10kHz RC oscillator calibration failed PLL calibration for receive failed PLL calibration for transmit failed
Comment PLL out of lock on startup (RX, TX, Sniff, Burst)
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
6.4.5.2.
Status/Flag2
The Status2 register provides information on the operating status of the part. The busy bit is asserted for any of the following reasons: Calibration: The busy bit will remain high for the duration of a calibration sequence. Status2 can be repeatedly polled during a calibration sequence to determine when it's complete. Read/Write EE: While the AMIS-53050 is reading from or writing to the EE, the busy bit will remain set. Buffered RX: When in the receive mode and a valid chip ID is found, the AMIS-53050 will begin the processing of this packet. During the time the packet is being processed, the busy bit will be set high. Buffered TX: After the command is given for transmit with the buffered packet option enabled, the busy bit will remain high until the part has completed the actual transmission of the packet. Housekeeping: Busy is asserted during a housekeeping cycle. Burst TX: Busy is asserted during a burst transmission. Status2 also contains information on the reason an interrupt was issued to the external host. The CCA channel status bits provide information back to the host on which channel within the multi-channels is being used for communication. After a CCA enabled transmission, these bits will be set to indicate which channel was used. For multichannel enabled receivers performing multi-channel sniff, these bits are used to indicate the channel upon which either energy or an entire packet was found. When the CCA is enabled, Bit 0 (CCA failed) is used to indicate whether or not the channel is clear. The flags will be reset when the register is read.
Table 29: Status/Flag2 - 0X02 [2] Bit Name State CCA Channel 7:4 [3:0] 111 110 101 Interrupt type 100 3:1 011 010 001 000 1 0 Busy 0
Comment Indicates channel selected during CCA RX CRC failed Receive energy dwell timer timed out CCA failed Transmit complete Buffer data for TX Data has been received Housekeeping Low battery AMIS-53050 is busy
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
6.4.5.3.
Software State
Software state displays the current mode of the AMIS-53050. This status register can be used to monitor the activity of the AMIS53050.
Table 30: Software State - 0X3C [60] Bit Name State 1111 1011 1010 1001 1000 0111 Software state 7:0 0110 0101 0100 0011 0010 0001 0000
Comment Undetermined Startup Copying ROM data to registers Calibrating LNA Calibrating PLL Calibrating 10kHz oscillator Calibrating Quick Start (kicker) oscillator Reading EE data Writing EE data Idle Transmitting Receiving Standby
6.5 Receiver The AMIS-53050 receiver is designed for reception of on/off shift key (AM) or frequency shift key (FM) modulated signals. The receiver includes all the circuitry to recover data from either the OOK or the FSK modulated signal carrier. The receiver operates on fixed frequencies in the operating frequency range of 300 to 960MHz using an internal fractional N PLL to set the frequency. The receiver can reduce power consumption using the Sniff Mode to acquire the incoming signal. The receiver can set a user defined fixed threshold for data detection or it can form a threshold from the incoming signal for determining the presence of signal and the state of the recovered waveform. The receiver can use a synchronous data detector to extract the data clock and the data from the incoming signal (FSK modulation always uses this method of data detection). OOK modulation (AM) o Manchester encoding option (600bps to 9.6kbps data rates) o CDR data detection option (recommended that this be used) o Common data rates from 1.2kbps to 19.2kbps or user defined FSK/GFSK modulation (FM) o Manchester encoding (600bps to 64kbps data rates) o FFT or PLL demodulation (depends on data rate) o Common data rates from 1.2kbps to 128kbps or user defined The AMIS-53050 receiver is a low IF frequency single down conversion, sub-sampling, image rejection architecture with a common AM/FM IF chain. Three demodulators are used for signal detection with additional post-detection and filtering capabilities for data recovery. A complex FFT demodulator is used for FSK signals with data rates > 20kbps. A digital PLL demodulator is used for FSK signals with data rates less than 20kbps. A logarithmic (RSSI) detector is used for OOK/ASK signals.
6.5.1. Receiver Circuit Brief Overview Clock and Data Recovery: The AMIS-53050 can extract a synchronous clock signal from the received data. In this mode, the data in the received signal is detected, filtered and then fed into the clock and data recovery block where additional digital filtering is performed. The waveform is sampled using a data clock in the AMIS-53050 to synchronously recover the data. Signal sensitivity is improved and the recovered data jitter is reduced by this method.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
LO Frequency: A sub-sampling LO frequency architecture is implemented that down converts the incoming RF signal to the IF frequency of about 500kHz. The LO frequency is produced from the internal VCO frequency. The frequency design of the LO signal reduces the power consumption of the AMIS-53050 and simplifies the receiver, achieving reliable, quadrature LO signal generation. IF Topology: The receiver implements a quadrature down-conversion architecture improving image rejection and creating the signals required for the complex FFT FSK signal detection. The receiver uses this quadrature down-conversion and a combination of passive and active poly-phase filtering to provide image suppression. Sniff Signal Acquisition: As with earlier ASTRIC devices, the AMIS-53050 can reduce the receiver power requirements by implementing the Sniff Mode for RF signal detection. Sniff mode is a method using the Quick Start oscillator to quickly wake the receiver, check for signal energy and return to sleep or start the receive function. The Quick Start can start the receiver crystal oscillator in as little as 10 micro-seconds. Using this fast start time, the sniff mode can turn on the receiver, check for signal energy and return to sleep in as little as 130 micro-seconds. More information about this sniff mode is in Section 6.7.2.
Table 31: Receive Command Register Number (HEX) 0X00 0X10 Name Command Idle config Code 0X01 0X03 Bit 0
Function Instruction to place the AMIS-53050 into receive (remember that all parameters for receive must be set before issuing this command) Instruction to set the AMIS-53050 into the Idle Mode Enable sniff function when in Idle Mode
Register descriptions: RX Config- Options for the receiver must be set. RF Frequency- The RF frequency of the receiver must be configured. (See Section 6.4.1.1)
6.5.1.1. RX Configuration
Figure 36: Receiver Timing Chart
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AMIS-53050 Frequency Agile Transceiver
Table 32: Receiver Timing Symbol TPRE TE TID TLOP
Notes: 1. 2.
Data Sheet
Timing Min. MOD 0 0 1 Default
1
Comments Typ. MOD
1
Max.
Units D Bits The TX preamble should be made long enough to allow the receiver to acquire the signal The energy dwell timer should be set long enough to allow the receiver to 2 detect the energy The ID dwell timer should be set long enough to allow the receiver to detect 2 the chip ID or global ID The length of packet will turn the receiver off after the number of data bits is received
255 255 255
D Bits D Bits D Bits
Indicates the need for a preamble and the type of preamble is determined by the data modulation selected. The dwell timers need to be long enough to allow the receiver to stay active from the time it turns on due to energy and the time that the desired event occurs. However, if the dwell times are set to their maximum value, in the case of false energy detection or signal corruption, excessive power dissipation results
The RX config register is used to set options for receive mode operation. Wake on Energy: When enabled, the CDR circuit is held in reset until the energy threshold is met. This option can be used to make the normal receiver function to perform similar to sniff. The energy dwell timer is used to determine how long the receiver will stay on checking for energy (with FF in the energy dwell time register, the receiver will stay on until the threshold is met). Gate on Energy: This option can be used in FM receive mode only, and will gate the data interface while the energy on RSSI is below the energy threshold. LNA Mode: The LNA can be configured for the following performance: 1. Normal gain mode reduces the current requirement for the LNA, but will loose some gain or sensitivity. 2. High gain mode delivers the best sensitivity but increases the current requirement also. 3. Linear mode sets the LNA to have less sensitivity than the high gain mode and more sensitivity than the normal gain mode while requiring less current than the high gain mode.
AM_FM_RX: Sets the mode of operation for receive Force Multi-Channel: When this bit is set, the bits in Status/Flag2 register (which usually show which channel the radio is on) can be overwritten to force the AMIS-53050 to operate on a particular channel. Typically the sequence should be to: 1. Write register 0X0E bit 3 to force the AMIS-53050 into force multi-channel channel mode 2. Write register 0X02 bits [7:4] to select the channel frequency to use 3. Command the AMIS-53050 to transmit or to receive
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AMIS-53050 Frequency Agile Transceiver
Table 33: RX Config - 0X0E [14] Bit Name State 7 RSSI active 1 0 6 5 LNA mode[1:0] 4 3 2 1 0 Force channel AM_FM_RX Gate on energy Wake on energy Multi channel 1 0 11 10 01 00 1 0 1 0 1 0 1 Clock and data disabled until energy threshold met No operation defined Linear mode High gain mode Normal gain mode Force receive mode on a specific channel of the 9 defined channels (status/Flag2) AM receive mode FM receive mode Clock and data outputs gated for RSSIData Sheet
6.5.1.2.
Energy Threshold
Energy threshold sets the threshold for either wake on energy or sniff mode. If the automatic noise floor detection is enabled in sniff, the AMIS-53050 will overwrite the contents of this register each time a new threshold is calculated.
Table 34: Energy Threshold - 0X15 [21] Bit Name Comment 7:0 E_Threshold Energy detect threshold in DAC mode = E_THRESHOLD*7.8125mV
6.5.1.3.
Receiver Parameters
Figure 37: Receiver Sensitivity vs. Data Rate
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 38: RSSI Curve
6.5.1.4.
Data Recovery
Table 35: Receiver Configuration RX Configuration Registers 0X0E RX Config Bit 2 Mod 0X1F CDR Options A Bit 0 0 0 FM 1 PLL Demod FFT 0X0B Data Rate Format Bit 3 0 1 0 1 0 1 1
Notes: 1. 2. 3. 4. 5.
0X1E Filter Slice Bit 1:0 SLICE SLICE SLICE SLICE SLICE SLICE SLICE SLICE
2 2 2
Data Rage
Preamble
CDR
SOF
Code NRZ
1
>20k - 128k >20k - 128k <20k <20k 1k - 19.2k 1k - 19.2k 1k - 19.2k 1k - 19.2k
10Pattern 10Pattern 10Pattern All 1 or 0's CW CW CW CW
Yes Yes Yes Yes Opt Opt Opt Opt
3 3 3
No No
4
Man NRZ
1
No 0X55 0XAA 0X55 0X0A 0X55 0X0A
Man NRZ Man NRZ Man
2
3
2 2 2 2
7 7 7 7
0 1 AM
NA
6
NA
6
0 1
Long strings of 1's or 0's will degrade the performance of the CDR circuits. SLICE can use the parameters in Table 37. Yes indicates that CDR is always used to detect the data. (See Table 41 and Table 42 for CDR parameters) Manchester encoded data requires a SOF. A unique SOF (suggested 0x66) is used to bit-align the Manchester decoder to the recovered data. 0X55 or 0X0A SOF have the following requirements: 0x55 The following is suggested: It is suggested that CDR with fast phase alignment be enabled It is suggested that CDR with activity check be enabled with 8 or 16 bit times It is suggested that the preamble be long enough to trigger activity check (10 or 20 bit times) 0x0A The following is suggested: It is suggested that CDR with fast phase alignment be enabled It is suggested that CDR with activity check be enabled with 4 bit times It is suggested that the preamble be long enough to trigger activity check 6. NA indicates that the parameter is not available for the AM/OOK modulated signals. 7. OPT indicates that CDR is an option to detect the data however, it is recommended that CDR be used. (See Table 41 and Table 42 for CDR parameters)
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AMIS-53050 Frequency Agile Transceiver
AM Data Recovery with RSSI
Data Sheet
The logarithmic AM detector, used with OOK/ASK modulated signals, produces an RSSI output signal with approximately 18mV/dB output level. A low pass filter provides additional filtering matched to the AM signal data rate (1.2, 1.8, 2.4, 4.8, 7.2, 9.6, 14.4, 19.2kbps). This filtered signal is sampled and compared to the slice threshold to recover the digital data. The slice threshold can be set to a fixed value or it can use a signal tracking circuit to set a peak or average threshold. The RSSI output signal can also be applied to a clock and data recovery circuit, which synchronizes an AMIS-53050 internal clock with the incoming data rate (see CDR Operation). Register descriptions: Slice Threshold- The slice operation needs to be selected, fixed or automatic. The value for the fixed threshold needs to be set. Filter/Slice- Filter settings and slice mode need to be selected.
Slice Threshold
Sets the data slice level for AM reception. This threshold is used when the slice method sets in the AM data filter and slice options register is set to DAC.
Table 36: Slice Threshold - 0X1D [29] Bit Name Comment 7:0 SL_THRESH [7:0] AM slice threshold in DAC mode = SL_THRESH*7.8125mV
AM Data Filter and Slice Options
This register contains settings for determining the method of slicing for AM receive mode. AM_FILTER: Sets the post-detection filter bandwidth for RSSI during AM receive. These filter bandwidths are set for the corresponding data rates. These filter settings can also be used with custom data rates. AM_HYST: Sets the amount of hysteresis in the AM slice comparator. AM_SLICE: Used to select the method for providing a reference to the AM slice comparator. DAC Mode: This is a fixed threshold level programmed into the slice threshold register. Average Mode: This is an automatic threshold level where the AMIS-53050 sets the threshold level to the average level of the RSSI signal. An external capacitor is required on the PEAK pin to set a bandwidth for the low pass filter response of the averaging circuit. . Peak Mode: This is similar to the average mode, but only the highest level is determined from the incoming signal and the AMIS-53050 sets the threshold to a level 6dB lower than the peak value. An external capacitor on the PEAK pin determines a bleed off (discharge) rate for the peak detector circuit. The value of this capacitor is discussed in the application note "Setting up the AMIS-52100 Data Slicing Modes" which applies also to this AMIS-53050 parameter.
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AMIS-53050 Frequency Agile Transceiver
Table 37: AM Data Filter and Slice Options - 0X1E [30] Bit Name State Comment 000 RSSI filter bandwidth =300Hz 001 RSSI filter bandwidth = 600Hz 010 RSSI filter bandwidth = 1.2kHz 011 RSSI filter bandwidth = 2.4kHz [7:5] AM_FILTER[2:0] 100 RSSI filter bandwidth = 4.8kHz 101 RSSI filter bandwidth = 9.6kHz 110 RSSI filter bandwidth = 19.2kHz 111 RSSI filter bandwidth = 38.4kHz 4 NU 00 DAC mode: Slice threshold set in register 1Bh 01 Average mode: AM threshold set using averaging filter [3:2] AM_SLICE[1:0] 10 Peak detect mode: AM threshold set using peak detector 11 DAC mode: Slice threshold set in register 1Bh 00 0mV slice hysteresis 01 25mV slice hysteresis [1:0] AM_HYST[1:0] 10 50mV slice hysteresis 11 100mV slice hysteresis
Data Sheet
FM FFT
The AMIS-53050 receiver uses a FFT function to recover data from a FM/FSK modulated signal when the data rate is higher than 20kbps. The FFT detector uses a two-bit DFFT to demodulate the incoming IF signal. This circuit also uses the same clock recovery block (CDR) as the AM detector (see Section 6.1.4) to detect the data. A pattern of 1's and 0's is required as a preamble. A SOF is not required unless Manchester encoded data is used, requiring a unique preamble to bit-align the Manchester decoder to the recovered data. Register descriptions: Data Rate- Can be specified in the discrete data rate register, or specified as a 16-bit word for a user defined data rate (see Section 7.1.3). Peak Deviation- The peak deviation register stores the value to be used for both transmit and receive. In the FFT FM receive mode, this value is used to set-up the FFT bins (see Sections 6.4.1.5 and 6.4.1.6). FM PLL Detector Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed (issue the command ROM2REGs to have the AMIS-53050 determine these values). For user defined data rates, this value needs to be calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.) CDR Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed (issue the command ROM2REGs to have the AMIS-53050 determine these values). For user defined data rates, this value needs to be calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.)
FM PLL (Low Data Rate FSK)
The AMIS-53050 uses a PLL function to recover the data from a FM/FSK modulated signal with data rates 20kbps or lower. This circuit uses an A DPLL for demodulation, the output of which is fed to the AM CDR circuit to recover the clock, and additionally filter the output data. The preamble sent by the AMIS-53050 when configured as NRZ FM is a repeating sequence of 1's and 0's. This gives the CDR circuit and PLL demodulator sufficient edges to acquire lock. Hence, for the NRZ case it is unnecessary to include a SOF byte. In Manchester mode, the preamble is specified as all 1's (or 0's). This gives the clock recovery circuit the most edges for lock acquisition. However, due to the ambiguity of the preamble, a SOF byte is necessary for the Manchester decoding block. The suggested SOF for this is either #55h or #AAh. The length of preamble necessary for this mode is dependant upon the loop bandwidth for the clock recovery PLL.
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AMIS-53050 Frequency Agile Transceiver
Register descriptions:
Data Sheet
Data Rate- Can be specified in the discrete data rate register, or specified as a 16-bit word for a user defined data rate (see Section 7.1.3). Peak Deviation- The peak deviation register stores the value to be used for both transmit and receive. In the FFT FM receive mode, this value is used to set-up the FFT bins (see Sections 6.4.1.5 and 6.4.1.6). PLL Detector Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed (issue the command ROM2REGs to have the AMIS-53050 determine these values). For user defined data rates, this value needs to be calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.) CDR Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed (issue the command ROM2REGs to have the AMIS-53050 determine these values). For user defined data rates, this value needs to be calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.)
PLL Detector Loop Filter Setting
A program (helper.exe available from AMIS) has been created to aid in the design of loop filter settings.
Table 38: PLL Detector Loop Filter Setting - 0X2B [43] Bit Name Comment 7:0 PLL_CO [7:0] PLL loop filter setting
Table 39: Clock Recovery Loop Filter Setting - 0X2C [44] Bit Name Comment 7:0 CDR_CO [7:0] Clock recovery filter setting
6.5.1.5.
Clock and Data Recovery
The AMIS-53050 device performs clock and data recovery for both AM/OOK/ASK and FM/FSK signals. An internal clock in the AMIS-53050 is programmed to be nearly the same rate as the expected data rate in the incoming signal. This clock is then synchronized to the incoming data rate by extracting a clock from the data. This loop recovery method recovers data without much of the jitter and noise associated with wireless communication links. Before launching headlong into the operation of the detectors, and how to set them up, it is instructive to review the following related registers, set-up options and their functions. Register descriptions: Fast Phase Alignment: In both the AM and PLL based FM modes (lower data rate), the AMIS-53050 can be configured to quickly acquire phase lock on incoming data. The pattern necessary for the fast phase alignment is simply `1010'. This function can be enabled in the CDR options A register. With this function enabled, the CDR circuit will operate with minimum power consumption until the `1010' sequence is received. A 32-bit correlation is used to not only recognize the 1010 pattern, but also to instantaneously provide a phase correction to the clock recovery circuit allowing very fast (less than 4 bit) lock times locking the incoming data. Activity Check: This function can be used in conjunction with the fast phase alignment to reset the clock and data recovery block back into its minimal power consumption mode when no transitions are detected on the data line for a specified period. The check can be configured for 4, 8 or 16 bit times. Over-Sampling Clock (Ts Clock): All three detectors use the Ts clock as the sampling clock for the transition from analog to digital. This clock should be set to the highest rate possible, but not greater than 400x the data rate, to ensure adequate phase information. For the discrete data rates, this value is pre-programmed for those rates when the ROM2REGS command is issued. Data Rate Clamp: The data rate clamp restricts the clock recovery circuit from wandering when an actual signal is not present, and the phase error signals being generated come only from noise. Small fractional values for the clamp can lead to longer lock times since the clock recovery PLL may not be able to make as large of a correction as is necessary all at once.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Channel Clamp: This clamping circuit is used to hold the low data rate FSK PLL detector within the specified limits to prevent the PLL from wandering in the absence of signal.
CDR Operation
This circuit utilizes an all digital PLL (ADPLL) to recover the clock from the raw sliced data. The slicer output is integrated over a bit time to provide a phase error, and the sign of the integration is used to determine the data symbol. When using the AMIS-53050 in AM mode with any of the packet framing options enabled, it is necessary to have the SOF byte for proper start-up of the AM CDR circuit. It is recommended that the CDR is set up with the activity check, and fast phase alignment features enabled for the packet framing modes. The preamble that the AMIS-53050 will transmit in AM mode is CW, hence the SOF byte is used by the fast phase alignment feature in the CDR to acquire lock. The suggested SOF for AM NRZ format is #55h. This will provide the most transitions for the clock recovery circuit to acquire lock prior to the incoming packet. For Manchester operation, the suggested SOF is #0A. This will provide early transitions for phase lock, and 4 bits to align the Manchester decode. Because there are no transitions during the preamble in AM mode, the CDR relies on the fast phase alignment for acquiring lock. As this is the case, the length of the preamble can be quite short as long as the activity check is enabled. The preamble should be long enough to trip the activity detection circuitry such that the fast phase alignment circuit is reset at the beginning of the SOF. This guarantees that the fast phase alignment will kick in during the SOF. The suggested length for the preamble is 4 BT's for Manchester with activity check set to 4 BT's, and 10 or 20 for NRZ, with activity check set to 8 or 16 respectively. Note in the NRZ case, enabling activity check will require the data be formatted to guarantee at least one transition in the data during the length of activity check (i.e. every 8 or 16 BT's). Register descriptions: ID Dwell- Set a time that the CDR circuit will continue to search for the chip ID. CDR Config- Set the parameters for the clock and data recovery circuits. Data Rate- Can be specified in the discrete data rate register, or specified as a 16-bit word for a user defined data rate (see Section 7.1.3). Start of Frame- Byte used to tell the AMIS-53050 receiver that data will start (see Section 7.1.6) CDR Loop Filter- For the discrete data rates, the values for the loop filter coefficients are pre-programmed (issue the command ROM2REGs to have the AMIS-53050 determine these values). For user defined data rates, this value needs to be calculated. (AMI Semiconductor provides a program, helper.exe, which can help in determining the values for this register.)
Chip ID Dwell Timer
Used to specify how long the clock and data recovery circuit will stay active after energy has been detected, looking for a valid chip ID. The part will look for either the chip ID or the global broadcast ID.
Table 40: Chip ID Dwell Timer - 0X14 [20] Bit Name Comment 00h: Code dwell timer disabled (for standard receive wake on code) 7:0 C_DWELL [7:0] 01h - FFh: Code dwell time = C_DWELL*bit time * 8 CDR Options A
This register contains settings for determining the clock and data recovery parameters. DR_clamp: Limits the CDR frequency drift between data packets Channel_clamp: Restricts the bandwidth to the channel bandwidth Activity check: Sets a number of bit times that the CDR circuit will shut down if there is no data present Fast phase alignment: Forces the CDR circuit to quickly synchronize to the incoming data FM mode: The FM detector used in the receiver depends on the data rate of the incoming signal
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AMIS-53050 Frequency Agile Transceiver
Table 41: CDR OptionsA - 0X1F [31] Bit Name State 7,6 DR Clamp<1> 11 10 01 00 11 5,4 Channel clamp 10 01 00 11 10 01 00 1 0 1 0 Comment 1/64 1/32 1/16 1/8 +-150 +-100 +-50 The clamp restricts the PLL detector to only lock on signals that are within the specified window, centered +-500kHz of the IF frequency The clamp restricts the clock recovery PLL to +- the fraction selected of the frequency selected by the BaudCLK which prevents clock wandering between data packets
Data Sheet
3,2
Activity check <1>
1 0
FPA enable FM mode
+-16 Reset after 16 bit times of no activity Reset after 8 bit times of no activity Reset after 4 bit times of no activity Activity check disabled, clock recovery will always run The CDR circuit will perform fast phase alignment CDR always running PLL FFT
CDR Options B
The sample clock values are written from ROM with the discrete data rate selected. The sample rate should be as fast as possible without exceeding 400 samples per bit time.
Table 42: CDR OptionsB - 0X20 [32] Bit Name State 7 6 5 4 1 CDR reset NU NU NU 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 45kHz 90kHz 187.5kHz 375kHz 750kHz 1.5M 3M 6M 8M 12M 16M 24M 0
Comment CDR is held reset
3:0
Sample clock
Clock Recovery Loop Filter Setting
A program (AMIS-53CDRPLLCalc.exe available from AMIS) has been created to aid in the design of the CDR loop filter settings.
Table 43: Clock Recovery Loop Filter Setting - 0X2C [44] Bit Name Comment 7:0 CDR_CO [7:0] Clock recovery filter setting
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AMIS-53050 Frequency Agile Transceiver
6.6 Transmitter
Data Sheet
Figure 39: Typical Output Power vs. Power Register Setting*
*Note: Curve is for output matched to 50.
Table 44: Transmit Command Register Number (HEX) 0X00 Name Command Code 0X02
Function Instruction to place the AMIS-53050 into transmit (Remember that all parameters for transmit must be set before issuing this command)
The AMIS-53050 uses a switching class E power amplifier as the high power output driver. The high power PA can be bypassed to allow a high efficiency at a lower output power. The output drivers are turned on and off directly in AM/OOK/ASK data modulation. A direct modulation PLL is used to form the FM/FSK signal for transmission. The PLL loop runs at half of the desired transmit frequency to provide excellent On/Off ratio for AM, and to lower current consumption in the PLL. OOK modulation (AM) FSK modulation (FM) Burst mode transmit FM wave shaping High power and low power range Register descriptions: Data Rate- Can be specified in the discrete data rate register, or specified as a 16-bit word for a user defined data rate (see Section 7.1.3) RF Frequency- The RF frequency of the transmitter must be configured (see section 6.4.1) Output Power- Sets the RF output level for the AMIS-53050
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AMIS-53050 Frequency Agile Transceiver
Peak Deviation- The FM deviation must be set for FM operation (see section 6.4.1.5 and 6.4.1.6) TX Config- Options for the transmitter must be set. Preamble- Set a reasonable length of preamble to insure that the receiver can detect the signal. 6.6.1. TX Config General options for transmit. AM_FM_TX: Used to set the mode for transmit
Data Sheet
Shaping: When enabled, the FSK transitions are digitally shaped in the fractional N PLL with a pre-programmed sequence. The filter for the shaping is Gaussian with a BT=1. This reduces the high frequency content of the data waveform that modulates the carrier. ID for TX: This option specifies which ID the AMIS-53050 will transmit when the use ID bit in general options A is enabled. Global is used to transmit from one node to all devices. Chip ID will transmit from one node to only those devices that have the same chip ID Buffered TX: When this option is enabled in conjunction with use ID and LOP enable, the packet for transmission is loaded into internal RAM prior to the RF being enabled. Force Multi-Channel: When this bit is set to 1, bits[7:4] of Status2 can be written to force the transmitter to operate on a specific channel of the nine channels defined by the multi-channel configuration (this feature can operate on any RF frequency if the ROM2REGS command has been used to create nine channels). Clear Channel Assessment: When one of the CCA modes of operation are enabled, the AMIS-53050 will enable its receiver to first check for the presence of energy on the specified channel before transmitting.
Table 45: TX Config - 0X0F [15] Bit Name State 11 7,6 10 Clear channel 01 assessment 00 1 5 Force channel 0 4 3 2 1 0 Smooth turn on NU ID for TX Shaping AM_FM_TX 1 0 1 0 1 0 Use the defined chip ID from the chip ID register Use the defined global ID from the chip ID register Gaussian FM data shaping enabled FM data shaping disabled AM transmit mode FM transmit mode 1 0
Comment Not allowed Multi-channel assessment (pre-defined channels) Single clear channel assessment prior to transmit (any frequency) No clear channel assessment performed, normal operation
Enable smooth power up of PA (reduces the spurious response of the TX on power up)
6.6.2. Output Power C_POWER: Coarse output power control for the power amplifier. When set high, the max out is 15dBm - when set low, the max output is 0dBm. F_POWER: Fine output power control for the PA. These seven bits control the voltage on the RFPWR pin via an internal DAC.F_POWER conversion output voltage.
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AMIS-53050 Frequency Agile Transceiver
Table 46: Output Power - 0X18 [24] Bit Name Comment 7 6:0 C_POWER F_POWER [6:0] Coarse output power selection sent to PA Fine output power control (upper 7 bits of the DAC, LSB of DAC=0)
Data Sheet
6.6.3. Preamble Length This byte is used to define the length of preamble to send prior to data in both transmit and burst mode transmit.
Table 47: Preamble Length - 0X1A [26] Bit Name Comment 7 PreambleLen [7:0] Length, in bit times, of CW (AM), or '10 (FM) sent prior to preamble in burst
Table 48: Suggested Preambles Modulation Preamble AM NRZ with CDR AM Manchester with CDR FM FFT FM PLL (NRZ) FM PLL (Manchester)
Notes: 1. 2. 3.
Comment SOF required and suggested as 0X55 SOF required and suggested as 0x0A No SOF is required No SOF is required SOF is required and suggested to be 55(Hex) or AA(Hex)
3 1 2
CW CW 1/0 pattern 1/0 pattern All 1s or 0s
When using SOF with NRZ data, it is suggested that fast phase alignment is enabled, activity check is set to 8 or 16 and preamble length is 10 or 20 bit times. When using SOF with Manchester coded data, it is suggested that fast phase alignment is enabled, activity check is set to 4 bit times and preamble length is set long enough to trigger the activity check. The length of this preamble is dependent on the loop bandwidth of the recovery clock PLL.
6.6.4. FM Transmit Data Shaping The AMIS-53050 allows the user to enable data shaping of the data waveform to improve the RF spectral efficiency. When enabled, the clock recovery NCO is used to provide an internal clock at 16 times the selected data rate. This clock is used to cycle through a predefined pattern whenever a transition is detected on the TX input. The shaping pattern is Gaussian with a BT=1. The intermediate values for the shaping are determined from the peak deviation register when an external host controller writes the `ROM 2 REGS' to the AMIS-53050 command register.
6.7 Idle
Table 49: Idle Command Register Number (HEX) 0X00 Name Command Code 0X03 0X04
Function Enable the idle state Return to idle state
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AMIS-53050 Frequency Agile Transceiver
Table 50: Idle Configuration Register Number (HEX) 0X02 0X0C 0X0D 0X10 Name Status/Flag2 General options A General options B Idle config Bits 0 2:1 0 1, 0 2 1 0
Data Sheet
Function AMIS-53050 is busy Select state that AMIS-53050 enters on POR Output system clock in standby mode Select the system clock frequency Enable housekeeping during Idle state Enable burst transmit operation during Idle state Enable sniff receive operation during Idle state
Note that there are two low-power modes for AMIS-53050 - standby and idle. Standby allows the SYSCLK output. Idle is the very low power state without SYSCLK output.
Table 51: Idle Modes Idle Tasks Sniff Burst transmit Housekeeping Standby Description Receiver periodic wake-up and RF energy detection check Periodic wake and transmit function Used to perform periodic temperature correction, calibration or to wake external host controller Low-power mode with no activity may be programmed to continue to output system clock
The AMIS-53050 allows for a low-power mode. Power requirements are reduced when the very low power 10kHz oscillator is the clock for the device. This oscillator runs the timers for either the sniff wake-up timer, the burst transmit timer or the housekeeping wake-up timer. However, even when the low power 10kHz oscillator is running, the AMIS-53050 can still provide a clock signal output to an external host controller device such as a microprocessor after reception of a valid data packet or a Housekeeping cycle where the AMIS-53050 has been programmed to issue a wake up to the external host controller. The AMIS-53050 will return to this low power idle state after activities such as transmit, receive or the various timers are done and the external host controller writes the `Return to Idle' instruction to the AMIS-53050 command register. Register descriptions: Idle Config- The options for idle mode must be set.
6.7.1. Idle Config The idle configuration register is used to specify which periodic tasks are performed once the idle command is given in register 0. Any combination of sniff, burst and housekeeping can be enabled. INT to DSSN Timing: This is the time between the AMIS-53050 issuing an interrupt to indicate that data is ready and the time that data transfer starts with the assertion of the DSSN signal. Idle to System Clock Stop: Once the AMIS-53050 has completed a task and is issued the idle command, the system clock can produce additional clock cycles to allow the external host controller to finish its tasks.
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AMIS-53050 Frequency Agile Transceiver
Table 52: Idle Config - 0X10 [16] Bit Name 7:5 Wait timing between INT and DSSN for sniff receive 4,3 Wait timing between idle instruction and system clock shutoff time Housekeeping Enable Burst enable Sniff enable State 111 ... 000 11 10 01 00 1 0 1 0 1 0 Periodic Sniff mode enabled (sniff settings must be set) Periodic burst mode enabled (burst settings must be set) Comment DSSN going active is delayed 8 bit times from INT DSSN is immediately active after INT System clock outputs 1024 clock cycles before shutdown after idle command System clock outputs 512 clock cycles before shutdown after idle command System clock outputs 256 clock cycles before shutdown after idle command System clock immediately shuts down after idle command Periodic housekeeping enabled (HK settings must be set)
Data Sheet
2 1 0
6.7.2. Sniff Mode Operation
Table 53: Sniff Mode Configuration Register Number (HEX) 0X0E 0X10 Name RX Config Idle Config Bits 1 0 2
Function Force the receiver to not output Clk&Data < energy level Set the receiver to wake when at energy level threshold Enable periodic sniff mode
The Quick Start technology enables the AMIS-53050 to operate its receiver in a mode called sniff mode. As implemented in the AMIS-53050, this sniff mode can wake the receiver and acquire the transmitted message in as little as 130 microseconds.
Figure 40: Sniff Waveform
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
The sniff mode of operation puts the AMIS-53050 receiver into a cyclic mode of sleeping and periodically waking to check for received signal energy. When energy is detected the receiver is placed in receive mode and the AMIS-53050 attempts to recover data. The receiver in sniff mode can be configured to check for a valid ID. The failure to receive a valid ID will cause the receiver to go back to sleep. The AMIS-53050 receiver average supply current can be estimated as:
Where,
is receiver current consumption in continuous receive mode, equal to or less than 12mA;
is receiver current consumption in sleep mode, equal to or less than 2uA; is programmable receiver energy scan impulse on time (sniff time), approximately equal to 130s minimum; is programmable receiver off time period length between receiver energy scan impulses (sniff mode interval). Register descriptions: Sniff Config-This sets the options in the sniff mode. Sniff Interval- Set the time interval between receiver wakeups in the sniff mode. Energy Threshold- The threshold for detecting the incoming RF energy must be set (see Section 6.5.1.2). Energy Dwell Time- Set the time interval that the receiver will remain active looking for RF energy detection. Code Dwell Time- Once RF energy has been detected the receiver can determine if the message has the unique ID for that receiver. The time interval for looking for this ID must be set (see Chip ID Dwell Timer). Threshold- The number of times a wake up is received can be monitored for false wake ups and the energy threshold adjusted to account for the noise level.
6.7.2.1.
Sniff Config
The Sniff config register is used to set additional options for the operation of the part during a sniff cycle, beyond those set in the RX config register. SNIFF_FILTER: Setting for the energy detection filter. This allows for different settings of the AM data filter between sniff and receive. The energy dwell timer needs to be extended long enough to allow for this filter to settle during the sniff cycle. Auto-Threshold Count Value: Number of sniff cycles used to determine whether to raise or lower the energy threshold for sniff. Any value other than 0x00 in this register will enable the auto-threshold function. Multi Channel: This bit enable the AMIS-53050 to scan the nine pre-defined channels defined by the multi-channel feature of the AMIS-53050. Sniff Interval Resolution: Determines the clock for the sniff interval timer.
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AMIS-53050 Frequency Agile Transceiver
Table 54: Sniff Config - 0X11 [17] Bit Name State 000 001 010 SNIFF_FILTER 011 7:5 100 101 110 111 11 4,3 Auto-threshold count value 10 01 00 2 1 NU NU Sniff interval resolution 1 0 Sniff interval timer resolution is 100ms (interval between sniff signal detection events is (sniff interval) times (sniff resolution) Sniff interval timer resolution is 500us (interval between sniff signal detection events is (sniff interval) times (sniff resolution) Comment RSSI filter bandwidth =300Hz RSSI filter bandwidth = 600Hz RSSI filter bandwidth = 1.2kHz RSSI filter bandwidth = 2.4kHz RSSI filter bandwidth = 4.8kHz RSSI filter bandwidth = 9.6kHz RSSI filter bandwidth = 19.2kHz RSSI filter bandwidth = 38.4kHz This is the number of Sniff cycles to count false wake ups due to the 100 noise level, so that the threshold level can be adjusted. It is 500 adjusted higher when the number of false wake ups exceeds the 100 wake up target number. It is adjusted down when there are fewer false wake ups than the target number. Entering a number other Disable than 00 in this register will enable the auto-threshold.
Data Sheet
0
6.7.2.2.
Sniff Interval Timer
This is used to specify the period (time between sniff events) of the sniff operation. The sniff interval is this value times the sniff interval resolution value (set in the sniff config register).
Table 55: Sniff Interval Timer - 0X12 [18] Bit Name Comment 7:0 SNIFF_INT [7:0] Sniff interval timer =SNIFF_INT* Sniff interval timer resolution
6.7.2.3.
Energy Dwell Timer
This is the length of time the receiver will stay on in a sniff cycle, checking for the presence of a signal. It is also used for a receive command when the wake on energy bit is asserted in RX config. This may need be set to a fixed value, such as 10 milli-seconds, to make the CCA compatible with a market or government standard.
Table 56: Energy Dwell Timer - 0X13 [19] Bit Name Comment 00h: Energy dwell timer not used, energy determined by an impulse sample 7:0 01h - FEh: Energy dwell time = E_DWELL * 100us E_DWELL[7:0] FFh: Receiver remains on until energy threshold is met
6.7.2.4.
Energy Threshold
This sets the threshold for either wake on energy or sniff mode signal acquisition. If the automatic noise floor detection is enabled in sniff, the AMIS-53050 will overwrite the contents of this register each time a new threshold is calculated.
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AMIS-53050 Frequency Agile Transceiver
Automatic Threshold Optimization in Sniff Mode
Data Sheet
An option available in the sniff mode config register will enable the AMIS-53050 to automatically adjust the energy threshold of the AMIS-53050 to optimize the sensitivity of the sniff mode. The target number of wake-ups (register 0X2F) allows the user to specify a value for the number of false wake-ups the AMIS-53050 is allowed with the selected configuration of the sniff mode (by bits [4:3] in the SNIFF_CONFIG register) number of sniff cycles. As an example: If the number of sniff cycles is set to 500 (sniff config [Bit 4:3]), If the target number of false wake-ups is set to 50 (target number wake-ups), Then over the course of the next 500 sniff cycles the radio is triggered falsely by energy: More than 50 times, the threshold will be increased to reduce the sensitivity, Less than 50 times, the threshold will be decreased to increase the sensitivity. Using this option to set the threshold for energy detection can have a dramatic impact on the life of battery powered devices. The AMIS53050 will adjust to changing levels of background noise while still maintaining maximum sensitivity and will not waste power by continually waking and processing background noise. Additionally, the energy threshold setting can be monitored by an external host controller. The amount the threshold will increase or decrease is based on Table 57, with the order of the rows in the same order as the AMIS-53050 will evaluate the conditions.
Table 57: Auto Threshold Adjust Condition Select the number of sniff cycles as the test period Enter the desired number of false wake ups per period Then if wake ups/period > target Then if wake ups/period < target Note: a false wake up is when the receiver detects energy but fails to detect the ID in the packet Threshold is increased Threshold is decreased Adjustment
The threshold of the AMIS-53050 can vary over a wide range from one device to the next, due to design, manufacturing tolerances, and environment changes; such as temperature and voltage. This automatic threshold optimization can be used to adjust the threshold by monitoring the level of false wake ups due to background noise. The adjustment in this fashion can reduce the effects of design and manufacturing on the threshold setting of the AMIS-53050. Register descriptions: Target- Set a value for the allowed number of false wake-ups desired.
Target Threshold
The number of false wake ups occurring during a period of time is used to automatically adjust the energy threshold in the sniff operation. This allows the AMIS-53050 to automatically adjust its input level to compensate for, manufacturing, components, environment, temperature and/or voltage.
Table 58: Target Wake Ups - 0X2F [47] Bit Name Comment The number of wake-ups that the sniff circuit will try to adjust the threshold to not have more false wake-ups or less missed signal detections. This register allows the number to 7:0 Target [7:0] be 0 to 255, but this number should always be less than the number of sniff count (sniff config bit 4:3).
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
6.7.3. Burst Transmit Data
Table 59: Burst Transmission Configuration Register Number (HEX) 0X10 Name Idle Config Bits 1
Function Enable burst transmissions
Burst mode of transmission is a function that can cause the AMIS-53050 to transmit a message at a programmed time interval or by asserting the xBURST pin to active (the AMIS-53050 must be in the xBURST mode), causing the AMIS-53050 to immediately transmit a message. The burst mode can also be started by enabling the burst mode in the idle register and then writing to the command register to set the AMIS-53050 into idle mode. The xBURST mode sets a timed automatic transmission of register values (a message) or ADC conversion values. Register descriptions: Burst Config- Set the burst transmission parameters Burst Interval- Set the time interval between burst transmissions User DataA- Message for timer initiated transmissions User DataB- Message for xBURST initiated transmissions.
Figure 41: Data Packet Format Showing Order for Burst TX Content
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AMIS-53050 Frequency Agile Transceiver
Used to set the options for the burst mode of operation:
Data Sheet
R_BURST: These bits set the number of times the packet is to be repeated each burst interval. This can be used to increase the probability that all packets will get through when several burst transmitters are located in the same area. Send Chip ID: This option is included to allow for the operating case of having multiple transmitters sending to a single receiver or for one transmitter to send to one receiver. The multiple transmitters will need to be configured to send the global chip ID in the TX config options so that the receiver will wake on all transmitter's packet. Sending the chip ID as part of the payload allows a single transmitter to send to only that receiver which has the same Chip ID. Send Internal ADC Data: When enabled, the AMIS-53050 will perform conversions on the battery voltage and temperature sensor and includes these conversions as part of the packet payload. Send External ADC Data: When enabled, the AMIS-53050 will perform conversions on the two external ADC inputs and includes these conversions as part of the packet payload. Burst Interval Resolution: Used to define the clock frequency for the burst interval timer.
Table 60: Burst Config - 0X16 [22] Bit Name State 7 6 Reserved Reserved 1 0 1 0 00 01 10 11 1 0 1 0 1 0 1 0
Comment
5:4
R_BURST[1:0]
3 2 1 0
Send dhip ID Send Internal ADC Data Send external ADC data Burst interval resolution
Packet is sent one time Packet is repeated once Repeat interval* Packet is repeated two times Packet is repeated three times Chip ID is included as part of the packet Data for temperature and battery is sent Data for EXT1, EXT2 is sent Burst interval timer resolution is 15s Burst interval timer resolution is 50ms
Note: When the burst transmission is repeated, the interval between transmissions is a random time period produced in a random number generator with the chip ID value used to seed the random number generator.
6.7.3.1.
Burst Interval
Burst interval defines the period for the normal burst transmission to occur. This is a cyclic mode and the AMIS-53050 will transmit the contents of a register at the end of each interval. This interval is fixed by the register value unlike the random time interval when the transmission is repeated.
Table 61: Burst Interval - 0X17 [23] Bit Name Comment 7:0 BURST_INT [7:0] Burst interval= (BURST_INT+1)*Burst interval resolution
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
6.7.3.2.
User Defined Data A
Table 62: User Defined Data A - 0X2D [45] Bit Name Comment 7:0 USE_DATAA [7:0] Optional data to be sent in normal burst mode if non-zero
6.7.3.3.
User Defined Data B
Table 63: User Defined Data B = 0X2E [46] Bit Name Comment 7:0 USE_DATAB [7:0] Optional data to be sent in interrupt triggered burst if non-zero
6.7.4. Housekeeping
Table 64: Housekeeping Enable Register Number (HEX) 0X10 Name Idle config Bits 0
Function Enable housekeeping timed functions
Housekeeping is another periodic operation mode, which can be used to periodically perform operations such as oscillator calibrations, PLL calibration, EE refresh or temperature compensation. It can also be used to periodically wake an external host controller to allow it to perform whatever tasks it may need to. The housekeeping configuration register contains the options to specify what is to occur during a housekeeping cycle, and the housekeeping interval timer is used to control how frequently the wake-up occurs. Register descriptions: Housekeeping Config- Sets the tasks for the housekeeping function Housekeeping Interval- Sets the time interval between times the AMIS-53050 wakes to perform the housekeeping function
6.7.4.1.
Housekeeping Config
The Housekeeping configuration register is used to specify which tasks the AMIS-53050 should perform during a Housekeeping cycle. HK Interval Resolution: Used to specify the clock frequency for the housekeeping interval timer Wake: When enabled, the AMIS-53050 will enable the system clock output, and issue an interrupt to an external controller. Write EE: This option is used to store the values of any calibrations that may have been performed during housekeeping. The entire working register bank will be written to EE. Read INT ADC Channels: The AMIS-53050 will do conversions on the battery voltage and temperature sensor. This can be used as a method to periodically update the temperature compensation loop. Read EXT ADC Channels: When enabled, the two external ADC inputs will be converted during a housekeeping cycle. Cal PLL, RC, Kicker: Allows periodic calibration of the oscillators of the AMIS-53050.
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AMIS-53050 Frequency Agile Transceiver
Table 65: Housekeeping Config - 0X1B [27] Bit Name State Comment HK interval 1 Five minute resolution setting 7 0 One second resolution setting resolution 6 5 4 3 2 1 0 Wake Write EE Read INT ADC channels Read EXT ADC channels Cal PLL Cal RC Cal kicker 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Kicker calibration performed during housekeeping RC oscillator calibration performed during housekeeping PLL calibration performed during housekeeping EXT1 and EXT2 ADC inputs converted Temp sensor and battery inputs converted Current register data written to EE (performed after all cal's complete)* Issue interrupt and enable clock to external host controller
Data Sheet
Note: * Bit 5 is set high to allow the EE to be automatically written after a calibration is complete.
6.7.4.2.
Housekeeping Interval
This sets the interval (time that the AMIS-53050 is in sleep mode) for the housekeeping routine.
Table 66: Housekeeping Interval - 0X1C [28] Bit Name Comment 7:0 HK_INT [7:0] Housekeeping interval = (HK_INT+1)* (HK interval resolution)
6.8 Idle Return
Table 67: Idle Return Register Number (HEX) 0X00 Name Command Code 0X04
Function In most conditions, the AMIS-53050 must be returned to idle mode at the end of a task by this command
This command is used to put the part back into idle mode. It should be used by the host to place the AMIS-53050 back into idle mode after the AMIS-53050 has interrupted the host for reception of a packet in sniff, or to end a housekeeping cycle.
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Data Sheet
6.9 EE The AMIS-53050 uses internal EE memory to store register settings (either default factory settings or user defined settings).
Table 68: Calibration Results Register Number (HEX) 0X00 0X01 0X1B Name Command Status/Flag1 Housekeeping Config Bits 0X05 0X06 2 5
Function Write the register contents to EE Read the contents of the EE EE checksum status Write register data to EE (automatic after calibration complete)
6.9.1. Write EE The serial interface provides a means to read and write the working registers of the AMIS-53050. To retain the information held by these registers, on-board EE is provided to store all of the register contents needed for operation. The write EE command copies the current contents of the working registers into EE, along with a CheckSum. The CheckSum is used to verify that the content of the EE is valid when the EE is dumped back into the registers.
6.9.2. Load EE The load EE command will refresh the contents of the working registers with the values stored in EE, if the EE CheckSum is valid. If the EE CheckSum fails an error bit will be set in the Status2 register.
6.10 Calibrate
Table 69: Calibration Results Register Number (HEX) Name Bits 0X07 0X00 Command 0X08 0X09 0X0A 6 0X01 Status/Flag1 5 4 3 0X1B Housekeeping config Kicker slope 0ptions 2 1 0 0X33 4
Function Perform a Quick Start oscillator calibration Perform a 10kHz RC oscillator calibration Perform a PLL calibration Perform a Quick Start oscillator calibration TX PLL calibration status RX PLL calibration status 10kHz RC oscillator calibration status Quick Start oscillator calibration status Perform the PLL calibration Perform the 10kHz RC oscillator calibration Perform the kicker calibration Kicker calibration status
Register descriptions: Trim- Shows the trim value for the circuit PLL Trim Target- Set a value that the PLL trim tries to achieve in calibration
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
6.10.1. Internal Trim
6.10.1.1. Crystal Trim Table 70: Crystal Trim - 0X21 [33] Bit Name Comment 7:0 XTAL_TRIM [7:0] 24MHz internal trim caps; FF is max capacitance, 00 is min
6.10.1.2. LNA Trim
The LNA trim requires that a known signal be applied to the AMIS-53050 receiver. Once a known signal is applied, the LNA selfcalibration can be run to determine the value for this register. The signal should be higher than minimum sensitivity. The LNA calibration uses this signal to trim the input and output as well as gain parameters to maximize the gain of the LNA.
Table 71: LNA Trim - 0X22 [34] Bit Name Comment 7:4 3:0 LNA_OUT[3:0} LNA_IN [3:0] LNA output tank cap trim F is max cap LNA input shunt capacitor trim, F is max, 0 is min
6.10.1.3. Quick Start Oscillator Trim
This register contains the value of the trim from the self calibration.
Table 72: Quick Start Oscillator Trim - 0X23 [35] Bit Name Comment 7:0 QS_TRIM [7:0] Trim for the Quick Start (kicker), this register is written to by the calibration circuit
6.10.1.4.
10K Oscillator Trim
This register contains the value of the trim from the self calibration.
Table 73: 10kHz Oscillator Trim - 0X24 [36] Bit Name Comment 7:0 RC_TRIM [7:0] Trim for the 10kHz oscillator, this register is written by the calibration circuit
6.10.1.5. Analog Trim1
This is an internal use register with no user-defined meaning. This register is set at the factory and changing the value will cause the AMIS-53050 to not operate.
6.10.1.6. Analog Trim2
This is an internal use register with no user-defined meaning. This register value is set at the factory and changing the value will cause the AMIS-53050 to not operate.
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6.10.1.7. RF PLL Trim
Data Sheet
This register contains the value of the trim from the self calibration. The values written to this register by the PLL calibration can provide some indication of the quality of the frequency selection. Values at the maximum or minimum allowed for the TX or RX trim function, even when calibration passes, may indicate (although not necessarily) that a different value for the VCO external LC components could provide better performance or that a slightly different frequency should be used.
Table 74: RF PLL Trim - 0X27 [39] Bit Name State 7 Max. VCO trim value from the self calibration 6:4 3 RX Mode PLL trim value 111 -000 Max. VCO trim value from the self calibration Min. VCO trim value from the self calibration TX Mode PLL trim value 111 --000 Min. VCO trim value from the self calibration
Comment
2:0
6.10.1.8. PLL Target Value
This register is used by the AMIS-53050 during self calibration. This is an internal use register with no user-defined function.
6.10.2. Calibrate Quick Start Oscillator The Quick Start oscillator must be calibrated prior to operations such as sniff or burst transmit. This command will perform an internal calibration of the oscillator, write the result to the Quick Start trim register, issue a calibration complete flag, as well as a calibration good/bad indicator. This command can be issued from any valid state that accepts changes in the instructions.
6.10.3. Calibrate 10kHz Oscillator In any of the idle modes of operation, an internal 10kHz oscillator is used as the timekeeping reference for the interval timers. The calibrate 10kHz oscillator command will enable the crystal oscillator to create an accurate time base to use for the calibration of this oscillator, and then perform the calibration and store the result. A cal done and status flag will be issued upon completion of the calibration. This command can be issued from any valid state that accepts changes in the instructions.
6.10.4. Calibrate PLL Calibrate the PLL performs a calibration for the PLL in both transmit and receive mode. The PLL status register reports the calibration value for both modes, as well as the status for the calibration. This command can be issued from any valid state that accepts changes in the instructions. This calibration is required when the AMIS-53050 is first powered on or returned from a device reset (before a transmit or receive instruction is issued).
6.10.5. Calibrate LNA This command turns on the RF receiver chain and optimizes both the LNA output tuning structure and the LNA input matching trim for maximum signal level on RSSI. This is a calibration typically performed at board assembly in the presence of a known RF signal. The AMIS-53050 will auto-tune both the input and output internal variable capacitances of the LNA to optimize gain, compensating for the tolerance of external components for the match. Note: Only perform this calibration with a known, non-modulated, signal input (the level should be high enough to be above the noise) input to the AMIS-53050 receiver.
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Data Sheet
6.11 ROM 2 REGS This command starts internal AMIS-53050 processes such as: Multi-Channel: Calculates the frequency information to form nine channels of 300kHz bandwidth. Four of these channels are at higher frequencies than the programmed RF frequency and four channels are at lower frequencies. Wave Shaping: Calculates the voltage steps to form the Gaussian wave shaping of the data for the data rate selected. Defined Data Rates: Calculates all the parameters for the selected data rate (selected from the defined data rates). RF Frequency: Calculates the parameters needed to set the TX/RX frequency AM Filters: Calculates parameters for the filter defined by the data rate selection (defined data rates).
6.12 Chip Reset This resets the entire chip, similar to a POR. This operation will reset the unlock test MUX register.
6.13 ADC Conversion
Table 75: ADC Configuration Register Number (HEX) 0X00 0X01 0X1B Name Command Status/Flag1 Housekeeping Config Bits 010xxxxx 110xxxxx 0 4 3
Function Perform a single ADC conversion (see Table 84) Perform continuous ADC conversions (see Table 85) The ADC conversion has completed Do an ADC conversion for the internal measurements Do an ADC conversion for the external measurements
The AMIS-53050 contains an 8 bit analog to digital converter. This ADC can measure the voltage on a number of internal functions, such as battery voltage, temperature, received signal strength indication voltage, and loop filter voltage. The results of these conversions are available through reading the registers where that data is stored or by using the feature of the burst transmission to send that information to another node. The AMIS-53050 also contains two ADC channels available on the device pins. The ADC can convert signals at a conversion rate up to 128k samples/second. Register descriptions: Temp- Contains the value from the last ADC of the internal temperature sensor. Battery- Contains the value from the last ADC of the internal battery voltage (divided by 2). RSSI- Contains the value from the last ADC of the signal level sample in the receiver. ADC1- Contains the value from the last ADC of the external analog input. ADC2- Contains the value from the last ADC of the external analog input. Loop Filter- Contains the value from the last ADC of the loop filter voltage.
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6.13.1. ADC Conversion Results
6.13.1.1. Temp ADC Table 76: Temp ADC - 0X34 [52] Bit Name Comment 7:0 TEMP_ADC [7:0] Temperature sensor ADC reading
Data Sheet
6.13.1.2. Battery ADC Table 77: Battery ADC - 0X35 [53] Bit Name Comment 7:0 BATT_ADC [7:0] Battery voltage ADC reading (Vbatt/2)
6.13.1.3. RSSI Table 78: RSSI - 0X36 [54] Bit Name 7:0 RSSI_ADC [7:0]
Comment RSSI voltage ADC reading
6.13.1.4. External Input 1 ADC Table 79: External Input1 ADC - 0X37 [55] Bit Name Comment 7:0 EXT1_ADC [7:0] External input 1 ADC reading
6.13.1.5. External Input 2 ADC Table 80: External Input2 ADC - 0X38 [56] Bit Name Comment 7:0 EXT2_ADC [7:0] External input 2 ADC reading
6.13.1.6.
Loop Filter
Table 81: Loop Filter - 0X39 [57] Bit Name Comment 7:0 LOOP_FILT [7:0] Internal loop filter
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6.13.2. Single ADC Conversion
Data Sheet
The single conversion command performs an ADC conversion on the channel specified as part of the command. Once complete, a flag is set, and the 8 bit data for the conversion is available in its associated register.
Table 82: Single ADC Conversions Register Number Bits Name (HEX) (7:6) 01 01 0X00 Command 01 01 01 01
Bits (5:0) 000001 000010 000100 001000 010000 100000
Function Perform an ADC on the external input 1 Perform an ADC on the external input 2 Perform an ADC on the internal temperature sensor Perform an ADC on the Internal battery voltage Perform an ADC on the receiver RSSI Perform an ADC on the loop filter
6.13.3. Continuous ADC Conversion This command can be given to the radio and operate in parallel with transmit or receive. This mode can also be entered into from an idle state. In this mode the specified ADC channel is continuously converted, and its associated register is continuously over written.
Table 83: Single ADC Conversions Register Number Bits Name (HEX) (7:6) 11 11 0X00 Command 11 11 11 11
Bits (5:0) 000001 000010 000100 001000 010000 100000
Function Perform continuous ADC on the external input 1 Perform continuous ADC on the external input 2 Perform continuous ADC on the internal temperature sensor Perform continuous ADC on the internal battery voltage Perform continuous ADC on the receiver RSSI Perform continuous ADC on the loop filter
7.0 Data Interface
Table 84: Control/Data Interface Physical Configuration Interface Function Clock Pin 3-wire Data DCLK DCLK 4-Wire Data DCLK DCLK Source Master Master Master Master Data Output DRXTX DRXTX DRXTX DRXTX Input DRXTX DRXTX DOPT DOPT DSSN DSSN DSSN DSSN Master Slave Master Slave Optional Buffered only Optional Buffered only Select AMIS-53050 Data Buffering
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Data Sheet
AMIS-53050
Figure 42: 3-Wire Serial Data Interface
AMIS-53050
Figure 43: 4-Wire SPI Compatible Serial Data Interface
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
The AMIS-53050 employs two different data interfaces. Transmit and receive data is exchanged with an external controller through either a 3-wire or a 4-wire SPI like interface. Selecting the interface, 3-wire or 4-wire is done by writing to Bit 7 of the general options B register. SPI serial data interface 3-wire serial data interface AMIS-53050 can be the slave or master Register descriptions: Chip Address- Allows a unique value to be transmitted and received with the data packet to identify a unique radio. Fixed Data Rates- Select the options for one of several fixed data rates. General Options A- Configure the interface options. General Options B- Configure the interface options. Idle Config- Sets a wait time between: 1. The INT signals a data transfer is ready and the DSSN line starts that transfer. 2. The Idle command and the SYSclk clock stops (allows for the external HOST controller to finish tasks). Start of Frame- Set a code value that indicates the start of a data packet. Preamble Length- Select a type of preamble and set the length in bits. (see Section 6.6.3) Custom Data Rates- Configures parameters for data rates that are not one of the fixed data rates. CRC Polynomial- Value of the CRC polynomial. Default Length of Packet- Set a default length for packets. Note: when the LOP or the default LOP (and the default LOP is enabled, bit 3 of the general optionsB register) is anything other than zero, the AMIS-53050 is in packet mode. Broad Cast ID- A general chip ID allowing for transmissions to be received by all radios. 7.1.1. Chip Address MSB1 The 16 bit ID that can be used for several purposes in the AMIS-53050 .
Table 85: Chip Address1 - 0X03 [3] Bit Name Comment 7:0 Chip_Add [15:8] Upper byte of chip address
7.1.2. Chip Address LSB
Table 86: Chip Address0 - 0X04 [4] Bit Name Comment 7:0 Chip_Add [7:0] Lower byte of chip address
7.1.3. Data Rate/Format The data rate/format register is used to select the data rate and format for both receive and transmit. The DDRATE[2:0} option bits allow selection of one of eight pre-programmed data rates. When one of the discrete data rates is selected, the ROM2REGS command is used to load clock and data recovery settings for the desired data rate into their associated registers.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
The Manchester option bit configures the AMIS-53050 to transmit and receive in the Manchester encoded format, while the data interface remains NRZ. If a data rate other than one of the available discrete rates is desired, the user should set the use custom bit, and then program the custom data rate register for the desired data rate. When the use custom data rate option is enabled, it is up to the user to set the correct sample clock frequency in the CDR options B register, set clock recovery loop filter settings, and if using the PLL based FSK detector, set the PLL detector loop filter. Note: For data rates that are near one of the pre-defined data rates, a discrete data rate could first be chosen, the ROM2REGS command given to load all of the settings for the various blocks for that data rate and then the custom data rate option enabled and the new data rate information entered. For example, if the desired data rate is 100kbps, set DDRATE to 110 for 96kbps operation. Next, issue the ROM2REGS command in the command register. All of the proper settings for the clock and data recovery circuit for a 96k data rate will be loaded into the working registers from ROM (sample clock frequency, clock recovery loop filter settings). Finally, enable the use custom option, and program data rate 1, and 0 with the value for a 100k data rate. Custom frequency is set in data rate 1 and data rate 0. If custom is 0, ROM contents for selected discrete data rate are loaded into data rate 1 and data rate 0.
Table 87: Data Rate/Format - 0X0B [11] Bit Name State Comment 7 6 5 4 3 NU NU NU Use custom Manchester 1 0 1 0 000 001 010 011 100 101 110 111 Manchester encoding selected NRZ encoding selected 1.2kbps 2.4kbps 4.8kbps 9.6kbps 19.2kbps 57.6kbps 96kbps 128kbps Enables user programmable data rate
2:0
DDRATE [2:0]
7.1.4. General Options A The general options A register contains a number of options that specify the operation of the part in its various modes. Standby Mode: Determines whether the crystal oscillator is enabled during standby. For applications relying on the AMIS-53050 to provide and external host controller with a system clock, this bit should be enabled, and is the default state. POR State: Specifies the power on state of the device. Once this has been stored into EE, the device will power up in the chosen state after the EE has been shadowed into the working registers. Pull up Disable: For applications not using an open drain type driver to drive the register interface pins (SDATA, SCLK and SSN) the pull-ups on these pins can be disabled via this option bit to save power. Temperature Compensation: When enabled, the ADC output for the temperature sensor is used to compensate the RF center frequency for crystal frequency error. A new correction factor is calculated each time the ADC performs a new conversion on the temperature sensor. CRC Enable: Enables internal CRC checking in RX, and appends a CRC in TX.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Length of Packet Enable: Allows buffering of packets, also allows CRC when enabled. The number of bytes to be sent is (N-1), where (N) corresponds to the value in the Default Length of Packet register. Note: When the default LOP or LOP value is anything other than zero (along with the Default LOP option bit enabled), the AMIS-53050 is in Packet mode. Use ID in RX and TX: When enabled, in receive mode the part will not output data until a valid ID is found, and in TX, the part will automatically send preamble and chip ID before enabling the data interface.
Table 88: General OptionsA - 0X0C [12] Bit Name State 7 6 5 4 3 Use ID in RX and TX Length of packet enable CRC enable Temperature compensation Pull-up disable 1 0 1 0 1 0 1 0 1 0 00 01 10 11 1 0 Standby Idle RX TX Crystal only mode, system clock output active Low-power standby mode RF center frequency temperature compensation enabled Temperature compensation is disabled Pull ups on IIC clock and data and SSN pins disabled Enables CRC (packet length must be enabled) Enables the part to frame packets
Comment Wake on ID in RX, send ID in TX
[2:1]
POR state
0
Standby mode
7.1.5. General Options B General options B contains more option bits for the general set-up and operation of the AMIS-53050. System Clock Output Frequency: Sets the frequency of the output clock on the SYSclk pin when enabled. RXTX Sampling Edge: Specifies which edge of DCLK should be used to sample the RXTX pin. Length of Packet Enable: This register defines the default LOP (register 0X31) so that the LOP does not have to be part of the data packet. This needs to be set to the same value in both the transmitting AMIS-53050 device and the receiving AMIS-53050 device, respectively. Note: When the default LOP or LOP value is anything other than zero (along with the Default LOP option bit enabled), the AMIS-53050 is in Packet mode. Data Interface Clock Frequency: Sets the clock frequency for the data interface when the AMIS-53050 is configured to be the master of the data interface. For modes in which the AMIS-53050 does not buffer the packet, the interface speed will always be the data rate, regardless of this setting. Data Interface Slave/Master: Specifies whether the AMIS-53050 is the master or slave for the data interface. 4-Wire Data Interface: Enables the 4-wire SPI data interface. When low, RXTX is bi-directional.
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AMIS-53050 Frequency Agile Transceiver
Table 89: General OptionsB - 0X0D [13] Bit Name 7 6 5,4 4-Wire data interface Data interface slave master State 1 0 1 0 11 10 01 00 1 0 2 RXTX sampling edge 1 0 11 1,0 System clock output frequency 10 01 00 AMIS-53050 is slave AMIS-53050 is Master, clock speed determined by bits 5, 4 1MHz 500kHz 100kHz Baud clock Data packet length is defined by the value of the default LOP register LOP must be sent with the data packet Data bits are sampled on the rising edge of DCLK on the interface Data bits are sampled on the falling edge of DCLK on the interface 12MHz (24MHz external crystal) 6MHz (24MHz external crystal) 3MHz (24MHz external crystal) Off Comment Enabled
Data Sheet
Data interface clock frequency
3
Default LOP
7.1.6. Start of Frame The start of frame byte is transmitted when this register is non-zero. It's used as an aid for the receiver clock and data recovery circuit in modes where the fast phase alignment feature is enabled. The data pattern required is different for different data modulations as discussed in Table 35.
Table 90: Start of Frame - 0X19 [25] Bit Name Comment 7:0 SOF [7:0] 8-bit code sent prior to chip ID in TX and burst
7.1.7. Data Rate 1 The data rate 1 and data rate 0 registers are used to set user defined data rates. These registers are loaded from ROM when a discrete data rate is selected. The following equation is used to calculate the value for CUST_DR:
where DataRate is the desired data rate, and Fsample_clock is the frequency selected for the sample clock. This register is loaded with the discrete rate if selected.
Table 91: Data Rate1 - 0X29 [41] Bit Name Comment 7:0 CUST_DR [15:8] Upper byte of user defined data rate/discrete data rate
7.1.8. Data Rate 0
Table 92: Data Rate0 - 0X2A [42] Bit Name Comment 7:0 CUST_DR [7:0] Lower byte of user defined data rate/discrete data rate
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
7.1.9. CRC Polynomial This register allows a designer to change the CRC polynomial used in the AMIS-53050. The register represents the presence of the powers in the CRC equation. For example: The polynomial x8+x5+x2+x+1 is encoded by assuming the polynomial will always have a high order bit. So the binary representation is: 1 0010 0111 This is set as the value 0X27 (HEX) in the register (See "Koopman, P. & Chakravarty, T., " Ccylic Redundancy Code (CRC) Polynomial Selection For Embedded Networks" DSN04, June 2004." for more information.)
Table 93: CRC Poly - 0X30 [48] Bit Name Comment 7:0 CRC_POLY [7:0] CRC polynomial value
7.1.10. Default Length of Packet This register allows a default value for the LOP (register value plus 1 byte) such that the AMIS-53050 does not have to send the LOP with a buffered packet.
Table 94: Default LOP - 0X31 [49] Bit Name Comment 7:0 DEFAULT_LOP [7:0] Default value for the length of packet to be used in buffered TX/RX
7.1.11. Broadcast ID 1 Many applications in the wireless market make use of a broadcast function where the Master note in a system can transmit to all wireless nodes in the network without addressing each node individually, but still not broadcasting to nodes in another network.
Table 95: Broadcast ID1 - 0X3A [58] Bit Name Comment 7:0 Global_ID1 [7:0] Lower byte of the global address
7.1.12. Broadcast ID 0
Table 96: Broadcast ID0 - 0X3B [59] Bit Name Comment 7:0 Global_ID0 [7:0] Upper byte of the global address
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
7.2 TX/RX Data Interface Protocol The AMIS-53050 TX/RX data format can be streaming data where the transmitter transmits each bit of data as it is received or it can be packetized. Packetized data can be in packets up to 256 bytes. Packetized data can add: a preamble, start of frame, identification code (Chip ID or Broadcast Global ID) length of packet, CRC error CheckSum.
Figure 44: Data Protocol Format
* Streaming or packetized data * Buffer size is 256 byte maximum * Packet overhead
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 45: Data Protocol Timing (AMIS-53050 as Master)
Table 97: Serial Data Timing Symbols TINT Tdssn TCLK TData TCend TDend Data Bit Description Interrupt to the external host controller to indicate data packet received Delay time from the interrupt to the time that DSSN is active low Time from DSSN going active and the start of the data clock Time from DSSN going active and the first bit of the data appears Time from the last clock pulse and DSSN goes inactive Time from the last data bit ends and the DSSN signal goes inactive Data bit period Typical 5 Register (Idle Config) Immediate Immediate Immediate Immediate Register (gen opts B) Clock period Units uS Bit times
Note: These times are when the AMIS-53050 controls the timing as the master. When the external Host controller is configured as the master, these times will change.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 46: 3-Wire Data Transfer Protocol
Figure 47: 4-Wire Data Transfer Protocol
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AMIS-53050 Frequency Agile Transceiver
Table 98: TX/RX Data Protocols Modulation AM FM (<20kbps) FM (>20kbps)
Notes: 1. 2. 3. 4.
Data Sheet
Detector RSSI PLL FFT
CDR Opt
1
Preamble CW 1 0 pattern
3
SOF Yes
4 2
ID/LOP/CRC See Table 99 See Table 99 See Table 99
Slice Fixed/Auto -------------------------
Yes Yes
-------
The use of the CDR function to recover the data is recommended for AM/OOK modulation. The SOF for AM modulation is suggested to be 55 (HEX) for NRZ and 0A (HEX) for Manchester encoded data. The preamble for FM (FFT) with NRZ data is a 1 0 repeating pattern. The preamble for FM (FFT) with Manchester encoded data is all 1s or all 0s. A SOF is only required for FM (FFT) when the data is Manchester encoded. The suggested SOF is a pattern of 55 (HEX) or AA (HEX).
Table 99: Interface Data Protocols TX/RX Data Protocol LOP N N Y Y
Note: 1. When the interface uses streaming data, the AMIS-53050 must be the master.
Interface Data Protocol Data Stream Stream Buffered Buffered
1
Comments
CRC N N N Y
Interface Active Active* Interrupt Interrupt
Data is streamed out the interface as it is received * Data is streamed out the interface starting with the wake-up on ID An interrupt is issued when data reception is complete An interrupt is issued when data reception is complete
The serial data interface for the AMIS-53050 can be configured to be: * A 3-wire interface or a 4-wire SPI interface * A master or a slave for both receive and transmit operation. * Data can be sampled on the rising, or falling edge of DCLK. The setting for the sampling polarity applies to all modes.
Table 100: Serial Data Interface Configuration General Options B Bit 7 0 0 1 1 X X Bit 6 0 1 0 1 X X Bit 2 X X X X 0 1 # Port Pins 3 3 4 4 X X AMIS-53050 Master Slave Master Slave X X Data Port Configuration Edge Sample X X X X Falling Rising Pin Function Definition DCLK Output Input Output Input DSSN Output Input Output Input DRXTX I/O I/O Output Output DOPT X X Input Input
7.2.1. AMIS-53050 in Master Mode In receive mode, the DSSN pin will transition low when the AMIS-53050 has received data. Immediately following the transition of DSSN, the AMIS-53050 will provide a synchronized bit clock on DCLK, and the received data will appear on DRXTX. In transmit mode, the transition of DSSN is used to signal an external host controller that the AMIS-53050 is ready for transmit data and is ready to receive that data on the DRXTX pin. Immediately following the transition of DSSN, the AMIS-53050 will provide a synchronous clock on DCLK for the host controller to use for loading transmit data into the AMIS-53050.
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AMIS-53050 Frequency Agile Transceiver
7.2.2. AMIS-53050 in Slave Mode
Data Sheet
The AMIS-53050 cannot be the slave for streaming data. The requirements of adding header information such as preamble or SOF requires that the AMIS-53050 be in control of the data interface transfer. The receiver has similar requirements with removing the header information. As the slave for the data interface, the AMIS-53050 will simply issue an interrupt to the external host indicating that data is available after a data packet has been received. For buffered transmit operation, the AMIS-53050 will issue an interrupt indicating it is ready to load the packet. After the packet is received by the AMIS-53050 and the transmitter is enabled, any packet formatting is done and the packet is sent.
7.2.3. Manchester Operation
Figure 48: Manchester Coded Data
If the Manchester option is selected in the data rate and format register, the AMIS-53050 will internally encode and decode both transmit and receive data respectively. The format for the signal interface remains NRZ in this mode.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
7.2.4. Packet Framing Three options bits located in the general options A register determine the method with which the transceiver will process packets: use ID, length of packet (LOP) enable and cyclic redundancy check (CRC) enable. An additional bit in the TX config register enables the buffered TX mode of operation.
Table 101: Register Configuration Bits General Options A Bit 7 0 Bit 6 0 Bit 5 0 TX Config Bit 3 0 Bit 2 X SOF All 0X00 non 0X00
1
Default LOP All X
Protocol
Comments
Streaming data
The preamble is transmitted and then data is transmitted as it is received The preamble and SOF are transmitted and then data is transmitted as it is received Preamble, ID is transmitted and then data is transmitted as received Preamble, ID, SOF is transmitted and then data is transmitted as received Packet is formed with Preamble, ID, LOP and data, then it is transmitted Packet is formed with Preamble, ID, SOF, LOP and data, then it is transmitted Packet is formed with Preamble, ID and data, then it is transmitted Packet is formed with Preamble, ID, SOF and data, then it is transmitted Packet is formed with preamble, ID, LOP and data, then it is transmitted with CRC at the end Packet is formed with preamble, ID, SOF, LOP and data, then it is transmitted with CRC at the end Packet is formed with preamble, ID and data, then it is transmitted with CRC at the end Packet is formed with preamble, ID, SOF and data, then it is transmitted with CRC at the end
0
0
0
0
X
X
Streaming data
1 1 1 1 1 1
0 0 1 1 1 1
0 0 0 0 0 0
0 0 0 0 1 1
1
opt opt opt opt opt opt
0X00 non 0X00 0X00 non 0X00 0X00 non 0X00 0X00
X X X X Value Value
Streaming data Streaming data Data packet Data packet Data packet Data packet
1
1
1
1
1
1
1
1
opt
opt
1
X
Data packet
1
1
1
opt
1
opt
1
non 0X00
X
Data packet
1
1
1
opt
1
opt
1
0x00
Value
Data packet
1
Notes:
1
1
opt
1
opt
1
non 0X00
Value
Data packet
X means that the register value is ignored (suggest setting the register to 0X00). Value means that the TX and the RX device will use default packets of length of this register plus 1 Byte. Optional means: General Options B; 1 means that LOP will not be transmitted but the Default LOP will be used 0 means that the LOP will be transmitted TX Config; 1 means that the Chip ID is transmitted 0 means that the Global Broadcast ID will be transmitted
7.2.5. Use ID
Table 102: ID Register Number (HEX) 0X0C 0X0F 0X16 Name General options A TX config Burst config Bits 7 2 3
Function Wake on ID in RX/send ID with TX Select either the chip ID or global ID to be used in transmissions Send ID with burst packet
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
The chip ID is a 16-bit word which can be programmed in registers three and four. In receive mode, when the use ID bit in general options A is set, the AMIS-53050 will not begin exporting or buffering data until a valid ID matching the value stored in the chip address registers is received. The ID is used in more advanced modes of operation for byte alignment. In addition to waking on its own unique ID, the AMIS-53050 will also wake on a pre-defined global chip ID. The default value for the global ID is in the register table. This value can be overwritten, but is not stored in EE so care must be taken when overwriting the value. With the use ID bit enabled in transmit mode, the AMIS-53050 will transmit the chip ID prior to enabling the data interface. An additional option bit in the TX config register allows selection of either the chip ID or global ID value for transmit. In either transmit or receive, when the use ID bit is enabled without LOP enabled, the AMIS-53050 will not buffer data. Hence when enabled stand alone, the data interface must be configured with the AMIS-53050 as the master.
7.2.6. Length of Packet Enable The length of the packet enable (LOP) bit located in general options A, enables the AMIS-53050 to buffer packets. The use ID bit must be used in conjunction with LOP to allow the receiver to byte align on incoming data. In receive mode with the LOP enabled, the AMIS-53050 will interpret the first byte following either a valid chip ID, or global ID to be the length of the incoming packet. This byte specifies the number of bytes following the LOP to be received (non-inclusive of the CRC if enabled). When enabled, the AMIS-53050 will buffer the incoming packet into internal RAM. Following reception of the last byte of the packet, an interrupt is issued on the interrupt pin, and depending on the configuration of the data interface, the packet will either be sent out of the data interface by the AMIS-53050 as master, or it will wait for the external host controller to stream the packet out as the master. LOP, in transmit mode, enables the buffering of the TX packet. Once the DSSN is pulled low by the AMIS-53050, the first byte received into the part is expected to be the LOP byte. Transmission continues until the AMIS-53050 has determined that all bytes have been received, at which point the data interface is disabled and the AMIS-53050 will return to standby. The actual loading of the data packet depends on the data interface setup as to whether the AMIS-53050 is master or slave.
7.2.7. CRC Enable The CRC enable located in general options A is the final tier of intelligence for the AMIS-53050 packet handling capability. In order for the AMIS-53050 to do CRC checking, this option must be used in conjunction with both use ID and LOP enable. Operation of the interface for both receive and transmit with the CRC enabled is no different from that explained under the LOP enabled section. With the CRC enabled, the AMIS-53050 will append the calculated CRC in transmit as the last byte. In receive mode, interrupts to the external controller will only be issued for packets passing the CRC.
7.2.8. SOF Byte
Table 103: Suggested SOF Modulation AM FM (<20kbps) FM (>20kbps) Detector RSSI PLL FFT Coding NRZ Manchester 1 0 pattern NRZ Manchester Preamble CW CW 1 0 pattern Repeating 1/0 All 1's or 0's SOF 55 (HEX) 0A (HEX) Not required Not required 55 (HEX) or AA (HEX)
Depending on whether the mode of operation is AM or FM, NRZ or Manchester, it may be necessary for a SOF byte to precede the chip ID. This byte is user programmable, and is used to ensure proper CDR operation and bit alignment prior to reception of the chip ID. When the contents of the SOF byte register are loaded to any non-zero value, this byte will be transmitted prior to the chip ID. For modes not requiring the SOF byte, setting this register to 00h will prohibit transmission of this byte. More information on when the SOF byte is required is in the clock and data recovery section.
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AMIS-53050 Frequency Agile Transceiver
7.2.9. Timing Diagrams for Various Packet Framing Modes
7.2.9.1. Use ID Enabled, No CRC, No Packet Length
Data Sheet
Table 104: Receive Parameter Action ID No LOP No CRC Data interface immediately ready after ID detected Radio stays in RX until instructed to change Data is shifted out data port as received Error checking is not performed and CRC is not attached to packet
Table 105: Transmit Parameter Action Transmit command immediately powers the transmitter on Transmit ID DSSN Transmits preamble AMIS-53050 returns to standby after Transmission completes Transmits the ID Starts data interface and uses a synchronous clock to clock in the TX data (Master only)
Figure 49: Data Interface Protocol (ID only)
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AMIS-53050 Frequency Agile Transceiver
7.2.9.2. Use ID Enabled, No CRC, LOP Enabled
Data Sheet
Table 106: Receive Parameter Action ID LOP Data interface immediately ready after ID detected Receiver loads rest of packet into buffer memory After last data byte is received, radio returns to the previous state An interrupt is issued to the external controller/microprocessor Data is transferred out the port with the AMIS-53050 as Master or the external controller as Master No CRC Error checking is not performed and CRC is not attached to packet
Table 107: Transmit Parameter Action Buffered If buffered transmit is selected, the AMIS-53050 will open the data interface and transfer all TX data Transmit into memory with AMIS-53050 as Master or external controller as master Transmit Transmit command (or end of TX data transfer) immediately powers the transmitter on Transmits preamble (length of preamble as specified) ID Transmits the SOF and the ID Starts data interface and uses a synchronous clock to clock in the TX data (master only) or clocks data out of memory (buffered TX) After the packet is transmitted, the transmitter returns to standby state
Figure 50: Data Interface Protocol (ID and LOP)
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AMIS-53050 Frequency Agile Transceiver
7.2.9.3. Use ID Enabled, CRC Enabled, LOP Enabled
Data Sheet
Table 108: Receive Parameter Action ID CRC LOP CRC invalid CRC valid Data interface immediately ready after ID detected As soon as the ID is validated, the CRC starts processing the data The LOP is received The rest of the received data packet is buffered into memory The last byte is the CRC and if invalid, the receiver waits for a command from the external host controller, or if the receiver came from idle it will return to receive Receiver returns to previous state and an interrupt is issued to the external controller The data interface is started and the data is sent to the controller, except for the CRC
Table 109: Transmit Parameter Buffered transmit Transmit ID CRC Action If buffered transmit is selected, the AMIS-53050 will open the data interface and transfer all TX data into memory with AMIS-53050 as master or external controller as master Transmit command (or end of TX data transfer) immediately powers the transmitter on Transmits preamble (length of preamble as specified) Transmits the SOF and the ID The CRC begins processing the data with the ID Starts data interface and uses a synchronous clock to clock in the TX data (Master only) or clocks data out of memory (buffered TX) The first byte is defined to be the LOP of the packet At the end of the packet, the data stops and the CRC value is sent After the packet is transmitted, the transmitter waits for a command from the external host controller
LOP CRC byte
Figure 51: Data Interface Protocol (ID, LOP and CRC)
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AMIS-53050 Frequency Agile Transceiver
8.0 General System Functions
8.1 Pull-up Disable
Data Sheet
2 The AMIS-53050 includes built in pull-up resistors for use with the I C operation to reduce the overall system component count. The pull-ups are asserted at POR until mode selection occurs. If the mode is determined to be 3-wire, the pull-ups are removed. If the mode 2 is determined to be I C, this option bit determines whether the pull-ups are to be removed.
2
Table 110: I C Pull Up Control Register Number (HEX) 0X0C Name General Options A Bits 3
Function Disable internal pull up resistors on I C bus
2
8.2 Brown-Out POR The brown-out POR serves two purposes. The first is to provide a POR signal to reset the digital when power is initially applied to the part. The second is to provide a POR should the voltage on the supply drift below normal operating range to prevent the AMIS-53050 from being placed in an unknown condition.
Table 111: Power-on-Reset Start Up State Register Number (HEX) Name Bits
Function 00 Standby
0X0C
General options A
2,1
01 Idle 10 RX 11 TX
8.3 Temperature Sensor
o The temperature sensor is created by using a Darlington pair of PNP transistors. The two transistors create a 5mV/ C slope, which can be sensed with an analog to digital converter. Without amplification, an 8 bit ADC with a 2V reference voltage will have a resolution better than two degrees.
The temperature sensor can be trimmed to an accuracy of 3C. As the trim is increased, the output voltage also increases. The temperature voltage relationship is given by:
Where V is the output voltage and T is the temperature in celsius. Register descriptions: ADC Temperature- Register shows the value of the temperature sensor ADC (see Section 6.13.1.1)
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
8.3.1. Crystal Temperature Compensation An on-chip temperature sensor combined with an on-chip A/D and a look-up table enable the part to maintain RF frequency accuracy within 2.5ppm over all operating voltages and temperatures (-45C to 85C). This function can be enabled via configuration Bit 4 located in general options A. When this function is enabled, a new calculation for the center frequency word will be performed whenever the temperature sensor storage register is updated with a new value. Therefore, it is possible to update the compensation value either in housekeeping, as part of a burst transmit cycle or as controlled externally by issuing the instruction to perform an ADC measurement of the temp sensor.
Table 112: RF Frequency Temperature Compensation Register Function Number (HEX) Name Bits 0X0C General options A 4 Enable RF frequency temperature compensation
8.4 Software The version of the AMIS-53050 is written to a register at the end of the manufacturing process. This code can help AMIS wireless product support when there is an issue with the AMIS-53050. Register descriptions: AMIS ID- Register contains a code showing the version of the AMIS-53050.
8.4.1. AMIS Part Revision Code
Table 113: AMIS Part Revision Code - 0X41 [65] Bit Name Comment 7:0 AMIS_ID [7:0] Revision status of the AMIS-53050
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AMIS-53050 Frequency Agile Transceiver
9.0 Built-in Test Functions
Data Sheet
The AMIS-53050 has a number of test registers. These registers are not available to the general user of the AMIS-53050. However, many of these registers control test features are useful in the development of applications using the AMIS-53050. Register descriptions: Test Unlock- A special code is required to unlock the functions of the test registers. Test- Registers that route signals to pins for monitoring or turn internal circuits off for test.
9.1 TM Unlock Register The developer designing the AMIS-53050 may desire to use some of the test modes to monitor the operation of the AMIS-53050 or to determine the activity of some parameter. These registers are locked from use by a code word. To unlock the test registers contact AMIS wireless product support to obtain the code. Enter this code in the unlock register to access the test registers. This register will be reset with a reset of the part and thus will lock the user out of the test registers. Register descriptions: Test Unlock- Register contains a code about the state the AMIS-53050 is operating in. ** Registers with the ** mark can be trimmed if the test registers are unlocked.
Table 114: Test Unlock Code - 0X40 [64] Bit Name Comment Code to unlock operation of the test registers (contact AMIS for the code to unlock the test register 7:0 UNLOCK [7:0] functions)
9.2 Test Registers The following registers allow for signals to be routed to pins for monitoring. They also turn functions in the AMIS-53050 on and off for measuring the operational parameters of the AMIS-53050.
9.2.1. IF Amp Manual Trim A This register is used for factory testing of the AMIS-53050 and has no user functions.
9.2.2. IF Amp Manual Trim B This register is used for factory testing of the AMIS-53050 and has no user functions.
9.2.3. PLL Manual Trim This register is used for factory testing of the AMIS-53050 and has no user functions.
9.2.4. PLL Test Modes This register is used for factory testing of the AMIS-53050 and has no user functions.
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AMIS-53050 Frequency Agile Transceiver
9.2.5. Power Down RF Sections This register is used for factory testing of the AMIS-53050 and has no user functions.
Data Sheet
9.2.6. Analog Test Mode Digital Pad Test: All digital pads except system clock out, and xInterrupt are 1mA I/O with pull ups and Schmitt triggers. The SYSclock and xInterrupt pads are 2mA outputs. Auto Increment Disable: This disables the automatic incrementing of the I2C register addresses. It can allow repeated writes to the same register, useful for adjusting a parameter to optimize its value.
Table 115: Analog Test Mode - 0X47 [71] Bit Name State Comment 7 6 5 4 3 2 CAP_TRIM Pipe ADC1 to data filter Brown-out power down Auto increment Disable Dither mode Ignore XTAL control 1 0 1 0 1 0 1 0 1 0 1 0 Enabled: 1 Dig pad test A 1 Ignore crystal control (digital clock gating) Dither is applied to the sigma-delta circuits in the PLL Address increment disabled (IIC only) Enable the ADC1 input channel as a direct input to the data filter Normal operation Override the brown-out POR to allow test at any voltage Enable the test mode for determination of capacitance trim value
0
Disabled Enabled:
0
Dig pad test B
1
0
Disabled
9.2.7. RF Test Modes This register is used for factory testing of the AMIS-53050 and has no user functions.
9.2.8. Analog Test MUX This register is used for factory testing of the AMIS-53050 and has no user functions.
9.2.9. RF Test MUX This register is used for factory testing of the AMIS-53050 and has no user functions.
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AMIS-53050 Frequency Agile Transceiver
9.2.10. Digital Test MUX A
Data Sheet
This register allows test signals to be routed to the indicated pins of the AMIS-53050. These signals can help in the development of an application using the AMIS-53050. The test unlock register code must be written, then this test register is written and then the test function will be enabled until either is changed or there is a reset of the AMIS-53050, even if the test unlock register code value is changed.
Table 116: Digital Test MUX A - 0X4B [75] Bit Test Pin Comment 1111 1110 1101 7:4 1100 MUX to SCLK 1111 - 0000 1011 1010 1001 1000 1111 1110 1101 3:0 1100 MUX to Dopt 1111 - 0000 1011 1010 1001 1000 Space Q channel CLK Mark Q channel CLK NC Data Q channel PN code from Start Analog data out PLL detect/data out Space I channel CLK Mark I channel CLK PLL detect/NCO out Energy detected Data I channel RF PLL CLK feedback Is locked (encoder) TX data 0111 0110 0101 0100 0011 0010 0001 0000 0111 0110 0101 0100 0011 0010 0001 0000 Energy dwell enable PLL increment TX enable 10kHz clock Software state [3] Bandgap ready ADC CLK Normal/system clock Code dwell enable PLL decrement Kicker PLL Z Software state [2] PLL xReset ADC power down D optional
9.2.11. Digital Test MUX B This register allows test signals to be routed to the indicated pins of the AMIS-53050. These signals can help in the development of an application using the AMIS-53050. The test unlock register code must be written, then this test register is written and then the test function will be enabled until either is changed or there is a reset of the AMIS-53050, even if the test unlock register code value is changed.
Table 117: Digital Test MUX B - 0X4C [76] Bit Test Pin Comment 1111 1110 1101 1100 7:4 MUX to xINT 1111 - 0000 1011 1010 1001 1000 1111 1110 1101 3:0 MUX to xBurst 1111- 0000 1100 1011 1010 1001 1000 Encoder in Decoder in Sniff output RF PLL (reference CLK) Brown-out output Receive done TS CLK Recovered clock Decoder out Encoder out CDR enable Baud clock (CDR out) CRC failed RX enable NC 0111 0110 0101 0100 0011 0010 0001 0000 0111 0110 0101 0100 0011 0010 0001 0000 Cal done kicker PLL in range INT0 Transmit done Software state [1] Xtal on ADC done xInterrupt PA enable PLL cal timer overflow PLL cal enable xtal PD Software state [0] isStopMode Watch dog reset xBurst
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AMIS-53050 Frequency Agile Transceiver
9.2.12. Digital Test MUX C
Data Sheet
This register allows test signals to be routed to the indicated pins of the AMIS-53050. These signals can help in the development of an application using the AMIS-53050. The test unlock register code must be written, then this test register is written and then the test function will be enabled until either is changed or there is a reset of the AMIS-53050, even if the test unlock register code value is changed.
Table 118: Digital Test MUX C - 0X4D [77] Bit Test Pin Comment 1111 1110 1101 7:4 MUX to Data SSN 1100 1111 - 0000 1011 1010 1001 1000 1111 1110 1101 1100 3:0 Reserved 1111- 0000 1011 1010 1001 1000 Undefined Undefined EE BIST good AM Filter Clock CPENA ROM BIST done ROM BIST bad RAM BIST done Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0111 0110 0101 0100 0011 0010 0001 0000 0111 0110 0101 0100 0011 0010 0001 0000 RAM BIST bad EE BIST done EE BIST bad Busy Instruction enable Bandgap power down XTAL DSSN Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
9.2.13. Digital Test Mode A This register is used for factory testing of the AMIS-53050 and has no user functions.
9.2.14. Digital Test Mode B This register is used for factory testing of the AMIS-53050 and has no user functions.
9.2.15. Digital Test Mode C This register is used for factory testing of the AMIS-53050 and has no user functions.
9.2.16. Digital Test Mode D This register is used for factory testing of the AMIS-53050 and has no user functions.
9.2.17. Memory Test Mode Address This register is used for factory testing of the AMIS-53050 and has no user functions. 9.2.18. Memory Test Mode Data This register is used for factory testing of the AMIS-53050 and has no user functions.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
10.0 Register Definition
Table 118 contains the addresses for all of the internal registers. Once the EE has been written, the POR states for the registers become the data last written. Should the CheckSum fail, all registers will return to the POR state shown and an error flag will be written to a status register.
Table 119: Register List Address R/W Hex Dec R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0X0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Register Name Command Status/Flag1 Status/Flag2 Chip address 1 Chip address 0 RF divider RF frequency 2 RF frequency 1 RF frequency 0 Peak deviation 1 Peak deviation 0 Data rate / format General options A General options B RX config TX config Idle config Sniff config Sniff interval Energy dwell time Code dwell timer Energy threshold Burst config Burst interval Output power Start of frame Preamble length HK config HK interval Slice threshold Filter/slice CDR options A CDR options B Crystal trim LNA trim Quick Start trim
Description Instruction register Part status, flags Part status, flags Upper 8 bits of chip address Lower 8 bits of chip address Integer portion of RF frequency Upper 8 bits of RF fraction Center 8 bits of RF fraction Lower 8 bits of RF fraction Upper 8 bits of FM deviation Lower 8 bits of FM deviation Set discrete data rate and encoding option General options for interface, POR state, etc. General options for interface, POR state, etc. Receiver options Transmit options Idle mode options Sniff mode options Interval between Sniff cycles Length of time to dwell in sniff mode Number of bit times to wait for code after energy detect Threshold for wake on RSSI, sniff and CCA Burst transmit options Interval timer for burst transmit Output power Byte used for burst transmit/CDR wake up Length of CW, or `10' repeated in Burst/TX (BT's) Housekeeping options register Interval timer for Housekeeping Energy threshold for AM DAC mode data slice AM/RSSI filter setting and AM slice mode Clock and data recovery options A Clock and data recovery options B Crystal trim LNA input and output matching trim Quick Start oscillator trim
POR State 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 1011_0100 0000_1010 0000_0000 0000_0000 0000_0000 0000_0000 0001_1000 0001_0000 0001_0000 0001_0000
EE
Section 6.2 6.4.5.1 6.4.5.2
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
7.1.1 7.1.2 6.4.1.1 6.4.1.2 6.4.1.3 6.4.1.4 6.4.1.5 6.4.1.6 7.1.3 7.1.4 7.1.5 6.5.1.1 6.6.1 6.7.1 6.7.2.1 6.7.2.2 6.7.2.3 6.5.1.5 6.5.1.2 6.7.3 6.7.3.1 6.6.2 7.1.6 6.6.3 6.7.4.1 6.7.4.2 6.5.1.4 6.5.1.4 6.5.1.5 6.5.1.5 6.10.1.1 6.10.1.2 6.10.1.3
1000_0000 0000_0000 0000_0000 0000_0000
X X X X
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AMIS-53050 Frequency Agile Transceiver
Table 118: Register List (Continued) Address R/W Register Name Hex Dec R/W 0x24 36 10k Osc trim 0x25 37 Analog trim 1 0x26 38 Analog trim 2 0x27 39 RF PLL trim 0x28 40 RF PLL options 0x29 41 Data rate 1 0x2A 42 Data rate 0 0x2B 43 PLL loop co 0x2C 44 CDR loop co 0x2D 45 User data 0x2E 46 User data 0x2F 47 TargNumWakeUps 0x30 48 CRCPoly 0x31 49 DefaultLOP 0x32 50 Checksum 0x33 51 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Temp ADC Battery ADC RSSI ADC EXT1 ADC EXT2 ADC Loop filter Broascast ID1 Broadcast ID0 Software state
Data Sheet
Description 10kHz oscillator trim Bandgap and temp sensor trim Capacitance trim PLL calibration storage register RF PLL options register User defined data rate upper bits User defined data rate lower bits User defined PLL detector bandwidth User defined clock recovery loop Transmitted on normal interval burst Transmitted on interrupt triggered Burst Target number of wake ups for CRC polynomial register Default LOP register EEPROM checksum Storage register for the temp sensor reading Storage register for the battery reading Storage register for the RSSI reading Storage register for the EXT1 input Storage register for the EXT2 input
POR State 0000_0000 0000_0000 0010_0100 0100_0100 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000
EE X X X X X X X X X X X X X X X
Section 6.10.1.4 6.10.1.5 6.10.1.6 6.10.1.7 6.4.1.7 7.1.7 7.1.8 6.5.1.4 6.5.1.5 6.7.3.2 6.7.3.3 6.7.2.4 7.1.9 7.1.10 6.9.1
0000_0000 0000_0000 0000_0000 0000_0000 0000_0000
6.13.1.1 6.13.1.2 6.13.1.3 6.13.1.4 6.13.1.5 Error! 7.1.11 7.1.12 6.4.5.3
Unlock reg AMIS ID code IF Amp trim A IF Amp trim B Manual PLL trim PLL Test Mode PDtestRF Analog test mode RFTM Analog test mux RF test mux Digital test mux A Digital test mux B Digital test mux C DTM A DTM B DTM C DTM D MTM address MTM data PLLCalTarget
1010_0101 0011_0001
Configure external pins as test signal Configure external pins as test signal Configure external pins as test signal
0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000
PLL calibration target value
0000_0000
9.1 8.4.1 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 9.2.10 9.2.11 9.2.12 9.2.13 9.2.14 9.2.15 9.2.16 9.2.17 9.2.18 6.10.1.8
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
11.0 Applications
This section intentionally left blank.
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AMIS-53050 Frequency Agile Transceiver
Data Sheet
12.0 Ordering Information
Table 120: Ordering Information Ordering Code Product Name Package Type 32 LQFP Operating Temperature Range -40C to 85C Industry Application Industrial, automotive, other Industrial, automotive, other Industrial, automotive, other Industrial, automotive, other Differentiating Feature Extra low power RX SPI interface; Ganged transceivers Extra low power RX SPI interface; Ganged transceivers Shipping Configuration Tape & Reel (-XTP); Tubes (-XTD) Tape & Reel (-XTP); Tubes (-XTD) Tape & Reel (-XTP); Tubes (-XTD) Tape & Reel (-XTP); Tubes (-XTD)
19608-001-XTP (or -XTD)*
AMIS-53050-I/A
19608-002-XTP (or -XTD)**
AMIS-53050-I/A
32 LQFP 32 LQFP, green/ RoHS 32 LQFP, green/ RoHS
-40C to 85C
19608-003-XTP (or -XTD)*
AMIS-53050-I/A
-40C to 85C
19608-004-XTP (or -XTD)**
AMIS-53050-I/A
-40C to 85C
* 19608-001 device will be deactivated and replaced by green/RoHS version 19608-003. ** 19608-002 device will be deactivated and replaced by green/RoHS version 19608-004.
13.0 Company or Product Inquiries
For more information about AMI Semiconductor, our technology and our products, visit our Web site at: http://www.amis.comU.
HTU TH
North America Tel: +1.208.233.4690 Fax: +1.208.234.6795 Europe Tel: +32 (0) 55.33.22.11 Fax: +32 (0) 55.31.81.12
Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS makes no warranty of merchantability or fitness for any purposes. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMIS for such applications. Copyright (c)2007 AMI Semiconductor, Inc.
AMI Semiconductor - Jan. 07, M-20639-002 www.amis.com
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